MyStorm.gise

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <!--                                                          -->

  <!--             For tool use only. Do not edit.              -->

  <!--                                                          -->

  <!-- ProjectNavigator created generated project file.         -->

  <!-- For use in tracking generated file and other information -->

  <!-- allowing preservation of process status.                 -->

  <!--                                                          -->

  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->

  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="MyStorm.xise"/>

  <files xmlns="http://www.xilinx.com/XMLSchema">
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="STORM_SoC_basic.bgn" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="STORM_SoC_basic.bit" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="STORM_SoC_basic.bld"/>
    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="STORM_SoC_basic.cmd_log"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="STORM_SoC_basic.drc" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="STORM_SoC_basic.lso"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="STORM_SoC_basic.ncd" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="STORM_SoC_basic.ngc"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="STORM_SoC_basic.ngd"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="STORM_SoC_basic.ngr"/>
    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="STORM_SoC_basic.pad"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="STORM_SoC_basic.par" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="STORM_SoC_basic.pcf" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="STORM_SoC_basic.prj"/>
    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="STORM_SoC_basic.ptwx"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="STORM_SoC_basic.stx"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="STORM_SoC_basic.syr"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="STORM_SoC_basic.twr" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="STORM_SoC_basic.twx" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="STORM_SoC_basic.unroutes" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="STORM_SoC_basic.ut" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:fileType="FILE_XPI" xil_pn:name="STORM_SoC_basic.xpi"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="STORM_SoC_basic.xst"/>
    <file xil_pn:fileType="FILE_NCD" xil_pn:name="STORM_SoC_basic_guide.ncd" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="STORM_SoC_basic_map.map" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="STORM_SoC_basic_map.mrp" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="STORM_SoC_basic_map.ncd" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="STORM_SoC_basic_map.ngm" xil_pn:subbranch="Map"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="STORM_SoC_basic_map.xrpt"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="STORM_SoC_basic_ngdbuild.xrpt"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="STORM_SoC_basic_pad.csv" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="STORM_SoC_basic_pad.txt" xil_pn:subbranch="Par"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="STORM_SoC_basic_par.xrpt"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="STORM_SoC_basic_summary.html"/>
    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="STORM_SoC_basic_summary.xml"/>
    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="STORM_SoC_basic_usage.xml"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="STORM_SoC_basic_xst.xrpt"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
  </files>

  <transforms xmlns="http://www.xilinx.com/XMLSchema">
    <transform xil_pn:end_ts="1424739492" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1424739492">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1424739492" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4184431762813159641" xil_pn:start_ts="1424739492">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1424739492" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2107557833123529570" xil_pn:start_ts="1424739492">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1424739492" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1424739492">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1424739492" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2965054779765253989" xil_pn:start_ts="1424739492">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1424739492" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1424739492">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1424739492" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6390134365526846484" xil_pn:start_ts="1424739492">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1424739568" xil_pn:in_ck="3296181932615602419" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3231258986117156273" xil_pn:start_ts="1424739492">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="STORM_SoC_basic.lso"/>
      <outfile xil_pn:name="STORM_SoC_basic.ngc"/>
      <outfile xil_pn:name="STORM_SoC_basic.ngr"/>
      <outfile xil_pn:name="STORM_SoC_basic.prj"/>
      <outfile xil_pn:name="STORM_SoC_basic.stx"/>
      <outfile xil_pn:name="STORM_SoC_basic.syr"/>
      <outfile xil_pn:name="STORM_SoC_basic.xst"/>
      <outfile xil_pn:name="STORM_SoC_basic_xst.xrpt"/>
      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
      <outfile xil_pn:name="xst"/>
    </transform>
    <transform xil_pn:end_ts="1424739568" xil_pn:in_ck="7122765540277519960" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-85837125391310138" xil_pn:start_ts="1424739568">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1424739575" xil_pn:in_ck="3488114362649037016" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="527412274782848547" xil_pn:start_ts="1424739568">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="STORM_SoC_basic.bld"/>
      <outfile xil_pn:name="STORM_SoC_basic.ngd"/>
      <outfile xil_pn:name="STORM_SoC_basic_ngdbuild.xrpt"/>
      <outfile xil_pn:name="_ngo"/>
      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    </transform>
    <transform xil_pn:end_ts="1424739676" xil_pn:in_ck="4976593025703934969" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4756088955047530681" xil_pn:start_ts="1424739575">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="STORM_SoC_basic.pcf"/>
      <outfile xil_pn:name="STORM_SoC_basic_map.map"/>
      <outfile xil_pn:name="STORM_SoC_basic_map.mrp"/>
      <outfile xil_pn:name="STORM_SoC_basic_map.ncd"/>
      <outfile xil_pn:name="STORM_SoC_basic_map.ngm"/>
      <outfile xil_pn:name="STORM_SoC_basic_map.xrpt"/>
      <outfile xil_pn:name="STORM_SoC_basic_summary.xml"/>
      <outfile xil_pn:name="STORM_SoC_basic_usage.xml"/>
      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
    </transform>
    <transform xil_pn:end_ts="1424739747" xil_pn:in_ck="-5626675044388695630" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1424739676">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="STORM_SoC_basic.ncd"/>
      <outfile xil_pn:name="STORM_SoC_basic.pad"/>
      <outfile xil_pn:name="STORM_SoC_basic.par"/>
      <outfile xil_pn:name="STORM_SoC_basic.ptwx"/>
      <outfile xil_pn:name="STORM_SoC_basic.unroutes"/>
      <outfile xil_pn:name="STORM_SoC_basic.xpi"/>
      <outfile xil_pn:name="STORM_SoC_basic_pad.csv"/>
      <outfile xil_pn:name="STORM_SoC_basic_pad.txt"/>
      <outfile xil_pn:name="STORM_SoC_basic_par.xrpt"/>
      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
    </transform>
    <transform xil_pn:end_ts="1424739776" xil_pn:in_ck="7218110307350213117" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="5341574683187206424" xil_pn:start_ts="1424739753">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="STORM_SoC_basic.bgn"/>
      <outfile xil_pn:name="STORM_SoC_basic.bit"/>
      <outfile xil_pn:name="STORM_SoC_basic.drc"/>
      <outfile xil_pn:name="STORM_SoC_basic.ut"/>
      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
      <outfile xil_pn:name="webtalk.log"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
    </transform>
    <transform xil_pn:end_ts="1424739747" xil_pn:in_ck="-7035149760447078667" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1424739736">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="STORM_SoC_basic.twr"/>
      <outfile xil_pn:name="STORM_SoC_basic.twx"/>
      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
    </transform>
  </transforms>

</generated_project>