STORM_SoC_basic.bgn

Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '6slx9.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
   "STORM_SoC_basic" is an NCD, version 3.2, device xc6slx9, package ftg256,
speed -3
Opened constraints file STORM_SoC_basic.pcf.

Mon Feb 23 20:02:37 2015

/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 STORM_SoC_basic.ncd 

INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). 
   9K Block RAM initialization data, both user defined and default, requires a
   special bit stream format.  For more information, please reference Xilinx
   Answer Record 39999.
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable**             |
+----------------------+----------------------+
| DebugBitstream       | No**                 |
+----------------------+----------------------+
| ConfigRate           | 2**                  |
+----------------------+----------------------+
| StartupClk           | Cclk**               |
+----------------------+----------------------+
| DonePin              | Pullup*              |
+----------------------+----------------------+
| ProgPin              | Pullup**             |
+----------------------+----------------------+
| TckPin               | Pullup**             |
+----------------------+----------------------+
| TdiPin               | Pullup**             |
+----------------------+----------------------+
| TdoPin               | Pullup**             |
+----------------------+----------------------+
| TmsPin               | Pullup**             |
+----------------------+----------------------+
| UnusedPin            | Pulldown**           |
+----------------------+----------------------+
| GWE_cycle            | 6**                  |
+----------------------+----------------------+
| GTS_cycle            | 5**                  |
+----------------------+----------------------+
| LCK_cycle            | NoWait**             |
+----------------------+----------------------+
| DONE_cycle           | 4**                  |
+----------------------+----------------------+
| Persist              | No*                  |
+----------------------+----------------------+
| DriveDone            | No**                 |
+----------------------+----------------------+
| DonePipe             | Yes                  |
+----------------------+----------------------+
| Security             | None**               |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF**         |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| Partial              | (Not Specified)*     |
+----------------------+----------------------+
| Encrypt              | No*                  |
+----------------------+----------------------+
| Key0                 | pick*                |
+----------------------+----------------------+
| StartCBC             | pick*                |
+----------------------+----------------------+
| KeyFile              | (Not Specified)*     |
+----------------------+----------------------+
| drive_awake          | No**                 |
+----------------------+----------------------+
| Reset_on_err         | No**                 |
+----------------------+----------------------+
| suspend_filter       | Yes*                 |
+----------------------+----------------------+
| en_sw_gsr            | No**                 |
+----------------------+----------------------+
| en_suspend           | No*                  |
+----------------------+----------------------+
| sw_clk               | Startupclk**         |
+----------------------+----------------------+
| sw_gwe_cycle         | 5**                  |
+----------------------+----------------------+
| sw_gts_cycle         | 4**                  |
+----------------------+----------------------+
| multipin_wakeup      | No**                 |
+----------------------+----------------------+
| wakeup_mask          | 0x00*                |
+----------------------+----------------------+
| ExtMasterCclk_en     | No**                 |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1*                   |
+----------------------+----------------------+
| CrcCoverage          | No*                  |
+----------------------+----------------------+
| glutmask             | Yes*                 |
+----------------------+----------------------+
| next_config_addr     | 0x00000000*          |
+----------------------+----------------------+
| next_config_new_mode | No*                  |
+----------------------+----------------------+
| next_config_boot_mode | 001*                 |
+----------------------+----------------------+
| next_config_register_write | Enable*              |
+----------------------+----------------------+
| next_config_reboot   | Enable*              |
+----------------------+----------------------+
| golden_config_addr   | 0x00000000*          |
+----------------------+----------------------+
| failsafe_user        | 0x0000*              |
+----------------------+----------------------+
| TIMER_CFG            | 0xFFFF               |
+----------------------+----------------------+
| spi_buswidth         | 1**                  |
+----------------------+----------------------+
| TimeStamp            | Default*             |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | No**                 |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

There were 0 CONFIG constraint(s) processed from STORM_SoC_basic.pcf.


Running DRC.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE21_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE22_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE4_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE6_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE24_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE1_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE11_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE13_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE25_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE12_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE15_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE14_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE3_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE23_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE5_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
   default, may be incorrect and should not be used.  For more information,
   please reference Xilinx Answer Record 39999.
DRC detected 0 errors and 16 warnings.  Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "STORM_SoC_basic.bit".
Bitstream generation is complete.