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RISC-V
The Open-Standard Instruction Set Architecture
- 3.7k followers
- Zurich, CH
- https://riscv.org
- @risc_v
- info@riscv.org
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Repositories
Showing 10 of 60 repositories
- riscv-cheri Public
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
- riscv-memory-tagging Public
Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
- riscv-spmp Public
The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.
- composable-custom-extensions Public
This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
- riscv-docs-base-container-image Public
A base container image populated with the dependencies to build the RISC-V Documentation.
