One place for all the default credentials to assist the Blue/Red teamers identifying devices with default password 🛡️

A FPGA friendly 32 bit RISC-V CPU implementation

⭐ ⭐ Distributed tcpdump for cloud native environments ⭐ ⭐

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

The Ultra-Low Power RISC-V Core

The SOC Analysts all-in-one CLI tool to automate and speed up workflow.

A collection of sources of documentation, as well as field best practices, to build/run a SOC

Awesome Security lists for SOC/CERT/CTI

The extensible bootloader for embedded system with application engine, write once, run everywhere.

RISC-V Linux SoC, marchID: 0x2b

学习安全运营的记录 | The knowledge base of security operation

MasterParser is a powerful DFIR tool designed for analyzing and parsing Linux logs

Tenzir is the data pipeline engine for security teams.

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

常见的攻击行为监测特征及方法，涵盖端点和流量，未包含PowerShell和Sysmon。预祝运营生活愉快！

SIEM Tactics, Techiques, and Procedures

Awesome list of keywords and artifacts for Threat Hunting sessions

Vitis_Accel_Examples

A collection of PowerShell modules designed for artifact gathering and reconnaisance of Windows-based endpoints.