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Insights: llvm/circt
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27 Pull requests merged by 9 people
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[ImportVerilog] Incorporate block names to variable/instance names
#8680 merged
Jul 10, 2025 -
[FIRRTL] Fix inject-dut-hier deleting new top
#8678 merged
Jul 9, 2025 -
Add SitestBlackBoxLibrariesAnnotation; process in CreateSiFiveMetadataPass
#8670 merged
Jul 9, 2025 -
[Datapath] Conversion Pass Comb to Datapath
#8664 merged
Jul 9, 2025 -
[ImportVerilog] Add support for SVA declarations
#8656 merged
Jul 9, 2025 -
[FIRRTL] Lint XMRs in the "design"
#8668 merged
Jul 9, 2025 -
[AIG][Python] Add Python bindings for LongestPathAnalysis
#8659 merged
Jul 9, 2025 -
[RTG] Add LowerValidateToLabels pass
#8666 merged
Jul 8, 2025 -
[FIRRTL] Delete BlackBoxResourceFileNameAnno
#8669 merged
Jul 8, 2025 -
Convert to CF before running LLHD inline.
#8667 merged
Jul 8, 2025 -
[importverilog] Lvalue RangelSelect and ElementSelect to use range.
#8663 merged
Jul 8, 2025 -
[LLHD] Make Deseq pass emit seq.firreg instead of seq.compreg
#8662 merged
Jul 8, 2025 -
[circt-synth] Add
-emit-bytecode
option#8661 merged
Jul 8, 2025 -
[seq] Simplify clock enabled when constant enabled.
#8655 merged
Jul 8, 2025 -
[LLHD] Add loop unrolling pass
#8620 merged
Jul 8, 2025 -
[PyCDE] Add bundle transform and rework coerce
#8660 merged
Jul 8, 2025 -
[ESI] Make RAM delarations' addresses unsigned
#8658 merged
Jul 7, 2025 -
[Datapath] Operator definitions and canonicalization patterns
#8647 merged
Jul 7, 2025 -
[PyCDE] Improve location information
#8635 merged
Jul 7, 2025 -
[RTG] Add EmbedValidationValuesPass
#8648 merged
Jul 7, 2025 -
[AIG][CAPI] Add C API for LongestPathAnalysis
#8652 merged
Jul 5, 2025 -
[AIG][NFC] Introduce a helper struct to manage result paths
#8651 merged
Jul 3, 2025 -
[AIG] Enhance longest path analysis with detailed timing statistics and JSON output
#8644 merged
Jul 3, 2025 -
[ExportVerilog] Add support for hw.array_inject
#8645 merged
Jul 3, 2025 -
[circt-verilog] Add MapArithToComb pass to pipeline
#8649 merged
Jul 3, 2025 -
[Python] Add Python bindings for AIG dialect
#8646 merged
Jul 3, 2025 -
[RTG] Add ValidationTypeInterface
#8639 merged
Jul 3, 2025
5 Pull requests opened by 4 people
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[MooreToCore] Lower exponentiation to math.ipowi (PowUOpConversion)
#8654 opened
Jul 7, 2025 -
Remove single state restriction on FSM to SV
#8665 opened
Jul 8, 2025 -
Insert probes at least post def.
#8674 opened
Jul 9, 2025 -
[RTG] Add Randomization Pipeline
#8675 opened
Jul 9, 2025 -
[circt-synth] [Synthesis] Add synthesis pipeline and refactor the lib structure
#8681 opened
Jul 10, 2025
5 Issues closed by 3 people
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[ImportVerilog] Incorporate block names into signal/instance names
#8679 closed
Jul 10, 2025 -
[ImportVerilog] Indexed ranges don't generate correct code
#8671 closed
Jul 9, 2025 -
[FIRRTL] Add InferTypeOpInterface to firrtl.int.ltl.* Operations
#8653 closed
Jul 8, 2025 -
Imported verilog flips output
#8657 closed
Jul 8, 2025 -
[FIRRTL] [Bug Report] Comb Loop Detect not aware of bitcast + extract
#8610 closed
Jul 6, 2025
5 Issues opened by 4 people
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Importing Verilog snippets and $finish equivalent in PyCDE
#8677 opened
Jul 9, 2025 -
Segmentation Fault During Constant Struct Initialization in PyCDE
#8676 opened
Jul 9, 2025 -
[LTL][SVA] Proposal for Explicit Clocking in the CIRCT LTL(SVA) Intermediate Representation
#8673 opened
Jul 9, 2025 -
[FIRRTL] BlackBoxTargetDirAnno not respected for all black boxes
#8672 opened
Jul 9, 2025 -
Move MapArithToComb into the Conversions directory
#8650 opened
Jul 3, 2025
4 Unresolved conversations
Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.
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[FIRRTL][CreateSiFiveMetadata] Add memory read-under-write behavior to emitted metadata
#8604 commented on
Jul 8, 2025 • 10 new comments -
[FIRRTL] Add "knownlayers" specifications to ExtModules
#8623 commented on
Jul 8, 2025 • 8 new comments -
[ImportVerilog] Bump `slang`
#7792 commented on
Jul 7, 2025 • 0 new comments -
[OM] Deprecate the OM map
#8606 commented on
Jul 9, 2025 • 0 new comments