Chisel Module that Processes Data

high-performance RTL simulator

Hardware design with Chisel

Implementation of the Advanced Encryption Standard in Chisel

AES implementations in chisel, PyRTL, VivadoHLS, C++ and Python

Chisel generator that renders the Mandelbrot set

A soft multimedia/graphics processor prototype in Chisel 3

RISC-V SoC designed by students in UCAS

An Adder written in Chisel

Bloom filter implemented in Chisel

A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).

Simple RISC-V 3-stage Pipeline in Chisel

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Berkeley's Spatial Array Generator

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Lipsi: Probably the Smallest Processor in the World

Sound effects and music related hardware (in Chisel)

A 256-RISC-V-core system with low-latency access into shared L1 memory.

A tiny POWER Open ISA soft processor written in Chisel

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

Open source machine learning accelerators

Example of composite video generation with Chisel (B/W for now)

A Chisel implementation of single-value Run Length Encoding (RLE)