🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Hardware implementation of the SHA-256 cryptographic hash function

Open Logic FPGA Standard Library

DPLL for phase-locking to 1PPS signal

Electric Dollar Store's open source repo

ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.

This repository contains reference implementations for various features of the Zynq Ultrascale+ MPSoC tested on the Mercury XU5 module from Enclustra.

A crude reverse engineering of the Pi5 PCIe connector & potential breakout boards.

FPGA-based I2C to RS-232 serial converter / bus monitor

Notes about specific FPGAs

HyperBus/HyperRAM Controller Core

simple hyperram controller

High Speed Data Acquisition over HDMI - Userspace library

A GUI for AVRDUDE

Source code of MIPI DSI Bridge Published on https://www.circuitvalley.com

Tutorial for BeeInvaders game on the Basys3 FPGA board

A book on using the Spartan 3E FPGA with VHDL, using the Papilio One or Digilent Basys2 boards

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

Simple fixed-cycle SDRAM Controller

An Inventory of mostly open-source Soft Core Processors. Although many have FPGA stats, many do not.

JTAG boundary scan debug & test tool.

GNU toolchain for RISC-V, including GCC

RISC-V implementation (r32i)

DisplayPort IP-core