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A web-based ASCII and Unicode diagram builder written in vanilla Javascript

OCRmyPDF adds an OCR text layer to scanned PDF files, allowing them to be searched

Repository for Marp Themes created with beauty and simplicity in mind.

🤙 Easy replacement for LaTeX Beamer! 🥂 custom Marp templates with a selection of over a dozen themes

A Datacenter Scale Distributed Inference Serving Framework

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Production-tested AI infrastructure tools for efficient AGI development and community-driven innovation

Teaching-focused digital circuit simulator

Fast and memory-efficient exact attention

RISC-V Opcodes

🌚 🌍 🌝 GeoIP 规则文件加强版，支持自行定制 V2Ray dat 格式文件 geoip.dat、MaxMind mmdb 格式文件、sing-box SRS 格式文件、mihomo MRS 格式文件、Clash ruleset、Surge ruleset 等。Enhanced edition of GeoIP files for V2Ray, Xray-core, sing-box,…

A modern formatting library

Run Windows apps such as Microsoft Office/Adobe in Linux (Ubuntu/Fedora) and GNOME/KDE as if they were a part of the native OS, including Nautilus integration. Hard fork of https://github.com/Fmst…

pytest plugin for toffee testing

Multi-platform nightly builds of open source digital design and verification tools

A framework for building hardware verification platform using software method

Awesome ASIC design verification

UCAS SEP扩展脚本 - 课程评估辅助 etc.

Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor

Collection of awesome vim9script plugins.

Open-source high-performance RISC-V processor

There is segmentation fault of VCS which should be fixed.

SystemVerilog language server

Pick your favorite language to verify your chip.

A rendition of everyone's favorite 1995 Microsoft operating system for Linux.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform