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@NYU-MLDA

NYU Machine-Learning guided Design Automation (MLDA)

Machine-learning aided Chip design

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  1. OpenABC Public

    OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

    Verilog 124 21

  2. ABC-RL Public

    This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.

    Verilog 5 1

  3. robust-pnr-time Public

    Implementation of ASPDAC 2021 paper: "Read your circuit: Leveraging word embedding to guide logic optimization"

    Verilog 5 2

  4. ALMOST Public

    ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning

    Verilog 2

Repositories

Showing 10 of 11 repositories
  • OpenABC Public

    OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

    Verilog 124 BSD-3-Clause 21 6 0 Updated Oct 10, 2024
  • ASCENT Public

    Side-channel aware RL-guided Logic Synthesis

    Jupyter Notebook 0 BSD-3-Clause 0 0 0 Updated Jul 14, 2024
  • ALMOST Public

    ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning

    Verilog 2 0 0 0 Updated May 13, 2024
  • ABC-RL Public

    This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.

    Verilog 5 GPL-3.0 1 3 0 Updated May 10, 2024
  • RTL_dataset Public

    Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys

    Verilog 1 BSD-3-Clause 0 0 0 Updated Feb 28, 2024
  • awesome-ml4co Public Forked from Thinklab-SJTU/awesome-ml4co

    Awesome machine learning for combinatorial optimization papers.

    Python 1 214 0 0 Updated Sep 5, 2023
  • explainable-ai-ic-testing Public
    0 0 0 0 Updated May 16, 2022
  • DIG Public Forked from divelab/DIG

    A library for graph deep learning research

    Python 0 GPL-3.0 288 0 0 Updated Mar 15, 2022
  • muzero-general Public Forked from werner-duvaud/muzero-general

    MuZero

    Python 0 MIT 636 0 0 Updated Mar 12, 2022
  • robust-pnr-time Public

    Implementation of ASPDAC 2021 paper: "Read your circuit: Leveraging word embedding to guide logic optimization"

    Verilog 5 BSD-3-Clause 2 0 0 Updated Mar 30, 2021
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