[TGRS 2024]Diff-Mosaic: Augmenting Realistic Representations in Infrared Small Target Detection via Diffusion Prior

[ECCV 2024] codes of DiffBIR: Towards Blind Image Restoration with Generative Diffusion Prior

The Compute Library is a set of computer vision and machine learning functions optimised for both Arm CPUs and GPUs using SIMD technologies.

😼 优雅地部署基于 clash/mihomo 的代理环境

Ultralytics YOLO11 🚀

SystemC Reference Implementation

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

Must-have verilog systemverilog modules

Verilog AXI stream components for FPGA implementation

Pytorch Implementations of large number classical backbone CNNs, data enhancement, torch loss, attention, visualization and some common algorithms.

A high-altitude infrared thermal dataset for Unmanned Aerial Vehicle-based object detection

Latex code for making neural networks diagrams

A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator

An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"

FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference

Tengine is a lite, high performance, modular inference engine for embedded device

FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud

NVDLA SW

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

An AXI DDR3 SDRAM controller for FPGA

YOLO Tutorial

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Verilog AXI components for FPGA implementation

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Rocket Chip Generator

📚 Collaborative cheatsheets for console commands

Implementation of BFGS within Python