Hardware Description Languages
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- bazel_rules_hdl Public
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
- constraints Public
Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
- containers Public
Building and deploying container images for open source electronic design automation (EDA)
- pyHDLParser Public Forked from kevinpt/hdlparse
Simple Python parser for extracting HDL (VHDL or Verilog) documentation
- conda-build-prepare Public
- conda-compilers Public
Conda recipes for C cross compilers needed for FPGA development with common processor architectures.
