User-friendly AI Interface (Supports Ollama, OpenAI API, ...)

Eine launige Einführung in Python

A simple 16bit system-on-chip (SoC) consisting of a CPU and GPU

PicoRV32 - A Size-Optimized RISC-V CPU

Master programming by recreating your favorite technologies from scratch.

A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark

High-performance eBPF implementation in hardware.

Material for paper "Fast Packet Processing with eBPF and XDP: Concepts, Code, Challenges and Applications", ACM CSUR 2019

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

The beginner's guide to eBPF

BCC - Tools for BPF-based Linux IO analysis, networking, monitoring, and more

P4 language tutorials

Material utilizado no minicurso "Processamento Rápido de Pacotes com eBPF e XDP" ministrado no SBRC 2019

Learning FPGA, yosys, nextpnr, and RISC-V

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

Userspace eBPF VM

hBPF = eBPF in hardware

A bit-serial CPU written in VHDL, with a simulator written in C.

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

👇 Add capacitive touch buttons to any FPGA!

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).