GF180MCU Test Structures by DanubeRiver

GF180MCU-C standard cell library test-design #2

GF180MCU-C standard cell library test-design

GF180MCU Test Structures by DanubeRiver - larger structures

Tapeout of NAND-Controller on GlobalFoundries 180nm Process Development Kit with Caravel from EFabless

Test Structures for GF180

MCP Server for Ghidra

SpinalHDL components for Corundum Ethernet

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https:/…

AXI interface modules for Cocotb

Simple runtime for Pulp platforms

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

System restore tool for Linux. Creates filesystem snapshots using rsync+hardlinks, or BTRFS snapshots. Supports scheduled snapshots, multiple backup levels, and exclude filters. Snapshots can be re…

riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

Open source FPGA-based NIC and platform for in-network compute

RAVA: an Open Hardware True Random Number Generator based on Avalanche Noise

Verilog Ethernet components for FPGA implementation

Blackwire SpinalHDL components implementing WireGuard primitives

A C++ implementation of ChaCha20 & Poly1305 stream cipher described in RFC - 8439.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

Optical lithography simulation software

Low level arithmetic primitives in RTL

🤗 smolagents: a barebones library for agents that think in python code.

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second

Creative Commons Licenses for Github

Fully local web research and report writing assistant

Verilog digital signal processing components