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RISC-V
The Open-Standard Instruction Set Architecture
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- riscv-smmtt Public
This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
riscv/riscv-smmtt’s past year of commit activity - riscv-performance-event-sampling Public
Define 2 new extensions to, along with Zihpm and Sscofpmf, enable event and instruction sampling with precise attribution.
riscv/riscv-performance-event-sampling’s past year of commit activity - riscv-cfi Public
This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
riscv/riscv-cfi’s past year of commit activity - riscv-cheri Public
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
riscv/riscv-cheri’s past year of commit activity - sig-functional-safety-whitepaper Public
GitHub repository for the Functional Safety SIG Whitepaper Development
riscv/sig-functional-safety-whitepaper’s past year of commit activity - riscv-memory-tagging Public
Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
riscv/riscv-memory-tagging’s past year of commit activity
