OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

KLayout Main Sources

A Python library for designing chips (Photonics, Analog, Quantum, MEMS), PCBs, and 3D-printable objects. We aim to make hardware design accessible, intuitive, and fun—empowering everyone to build the future.

SiEPIC EBeam PDK & Library, for SiEPIC-Tools and KLayout

KLayout Python library for integrated quantum circuit design.

gdsfactory plugins

KLayout technology files for Skywater SKY130

Primitives for SKY130 provided by SkyWater.

Python library for KLayout (https://www.klayout.de/)

KLayout technology files for FreePDK45

Simple 3D layout viewer for KLayout (Salt package)

Parametric NEM/MEM relay design with layout generation (KLayout: GDSII), FEM (Ansys/COMSOL), SPICE models, Liberty models, & more

Learn, share and collaborate on ASIC design using open tools and technologies

Conda + KLayout

A Python based PCELL generator and Layout generator for adiabatic bragg grating spirals.

Netlist extraction into SPICE format for KLayout.

Primitives for SKY90FD provided by SkyWater.

KLayout GIT Repository Manager

This repository offers custom PCells and functional macros for KLayout for LFL Lab Workflows