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[RISCV][NFC] Zce always implies/requires Zca #145442

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Merged
merged 1 commit into from
Jun 24, 2025

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lenary
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@lenary lenary commented Jun 24, 2025

According to the spec, Zce:

  • On RV32 without F: includes Zca, Zcb, Zcmp, Zcmt
  • On RV32 with F: includes Zca, Zcb, Zcmp, Zcmt and Zcf
  • On RV64: Zca, Zcb, Zcmp, Zcmt.

In these cases, Zce always implies Zca, Zcb, Zcmp, and Zcmt, so I have added it to the list of Implied/Required extensions, where it wasn't included before. The RV32f rule is implemented in RISCVISAInfo.cpp already.

This is NFC, because TableGen expands these implications transitively, which was eventually picking up Zca via any of the other three.

According to the spec, Zce:
- On RV32 without F: includes Zca, Zcb, Zcmp, Zcmt
- On RV32 with F: includes Zca, Zcb, Zcmp, Zcmt and Zcf
- On RV64: Zca, Zcb, Zcmp, Zcmt.

In these cases, Zce always implies Zca, Zcb, Zcmp, and Zcmt, so I have
added it to the list of Implied/Required extensions, where it wasn't
included before. The RV32f rule is implemented in RISCVISAInfo.cpp
already.

This is NFC, because TableGen expands these implications transitively,
which was eventually picking up Zca via any of the other three.
@llvmbot
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llvmbot commented Jun 24, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

Changes

According to the spec, Zce:

  • On RV32 without F: includes Zca, Zcb, Zcmp, Zcmt
  • On RV32 with F: includes Zca, Zcb, Zcmp, Zcmt and Zcf
  • On RV64: Zca, Zcb, Zcmp, Zcmt.

In these cases, Zce always implies Zca, Zcb, Zcmp, and Zcmt, so I have added it to the list of Implied/Required extensions, where it wasn't included before. The RV32f rule is implemented in RISCVISAInfo.cpp already.

This is NFC, because TableGen expands these implications transitively, which was eventually picking up Zca via any of the other three.


Full diff: https://github.com/llvm/llvm-project/pull/145442.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+2-1)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index e2204eba4c23f..36b3aff51cda9 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -455,7 +455,8 @@ def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
 def FeatureStdExtZce
     : RISCVExtension<1, 0,
                      "Compressed extensions for microcontrollers",
-                     [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>;
+                     [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
+                      FeatureStdExtZcmt]>;
 
 def HasStdExtCOrZcfOrZce
     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() ||"

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LGTM

@lenary lenary merged commit 0fcced7 into llvm:main Jun 24, 2025
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@lenary lenary deleted the pr/riscv-zce-zca-dep branch June 24, 2025 03:09
DrSergei pushed a commit to DrSergei/llvm-project that referenced this pull request Jun 24, 2025
anthonyhatran pushed a commit to anthonyhatran/llvm-project that referenced this pull request Jun 26, 2025
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3 participants