Parsing Issues

[kwmartin]

I'm not sure if Pyverilog is any longer being actively supported or upgraded? I have made quite a few modifications in order to parse my in-house standard digital library, and it would take some effort to incorporate these in the main branch. Some of these include:

1. Specify blocks are not handled. I have extended Pyverilog to handle the "Simple module paths - 14.2.2 in IEEE Std 1364-2001) that are used in my library - this has not been well tested but does include edge-sensitive state-dependent paths (pg 217 in IEEE Std 1364-2001) and full connection and parallel paths and multiple module paths in a single statement (pg. 220, Sect. 14.2.6)
2. The "or" sensistivities such as in:
   always @(posedge clk or reset) did not parse properly (note mixing an edge sensitive ID and a non edge-sensitive ID).
3. Multiple value assign statements, such as example 3 on pg 71 of IEEE Std 1364-2001, did not parse properly.
   Is there any interest in adding these changes? I have very little experience in starting new branches in git hub and then publishing them. From the previous issue, it appears udp's also need to be supported if we want to go forward. Bringing my changes in would involve committing quite a bit of time, and would negatively impact on-going projects, so it is dependent on this project being actively developed.

[shtaxxx]

Thank you for your suggestions. I think these problems should be fixed, but I could not take sufficient time for the development, unfortunately.