Merge pull request #4 from ilya-epifanov/risc-v

RISC-V support

Author: Disasm

Cargo.lock

@@ -1,6 +1,6 @@
 [workspace]
 members = [
-  "async-cortex-m",
+  "async-embedded",
   "cortex-m-udf",
   "nrf52",
   "panic-udf",

Cargo.toml

@@ -2,14 +2,25 @@
 authors = ["Jorge Aparicio <jorge.aparicio@ferrous-systems.com>"]
 edition = "2018"
 license = "MIT OR Apache-2.0"
-name = "async-cortex-m"
+name = "async-embedded"
 publish = false
 version = "0.0.0-alpha.0"
 
 [dependencies]
-cortex-m = "0.6.2"
-cortex-m-udf = { path = "../cortex-m-udf" }
 generic-array = "0.13.2"
 heapless = { git = "https://github.com/japaric/heapless", branch = "slab" }
 pin-utils = "0.1.0-alpha.4"
 typenum = "1.11.2"
+
+[target.'cfg(target_arch = "arm")'.dependencies]
+cortex-m = "0.6.2"
+cortex-m-udf = { path = "../cortex-m-udf" }
+
+[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
+riscv = "0.5.6"
+
+[features]
+default = ["riscv-wait-nop"]
+riscv-wait-nop = []
+riscv-wait-wfi-single-hart = []
+riscv-wait-extern = []

async-cortex-m/src/lib.rs

@@ -7,7 +7,6 @@ use core::{
     task::{Context, Poll, RawWaker, RawWakerVTable, Waker},
 };
 
-use cortex_m::asm;
 use heapless::Vec;
 use pin_utils::pin_mut;
 
@@ -120,7 +119,7 @@ impl Executor {
 
             // try to sleep; this will be a no-op if any of the previous tasks generated a SEV or an
             // interrupt ran (regardless of whether it generated a wake-up or not)
-            asm::wfe();
+            unsafe { crate::wait_for_event() };
         };
         self.in_block_on.set(false);
         val

async-cortex-m/Cargo.toml renamed to async-embedded/Cargo.toml

@@ -0,0 +1,102 @@
+//! Proof of Concept async runtime for the Cortex-M architecture
+
+#![deny(missing_docs)]
+#![deny(rust_2018_idioms)]
+#![deny(warnings)]
+#![no_std]
+
+mod alloc;
+mod executor;
+pub mod task;
+pub mod unsync;
+
+#[cfg(target_arch = "arm")]
+use cortex_m::asm;
+
+
+#[cfg(target_arch = "arm")]
+pub use cortex_m_udf::udf as abort;
+
+#[cfg(target_arch = "arm")]
+#[inline]
+/// Prevent next `wait_for_interrupt` from sleeping, wake up other harts if needed.
+/// This particular implementation does nothing, since `wait_for_interrupt` never sleeps
+pub(crate) unsafe fn signal_event_ready() {
+    asm::sev();
+}
+
+#[cfg(target_arch = "arm")]
+#[inline]
+/// Wait for an interrupt or until notified by other hart via `signal_task_ready`
+/// This particular implementation does nothing
+pub(crate) unsafe fn wait_for_event() {
+    asm::wfe();
+}
+
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+/// This keeps dropping into the debugger and never returns
+pub fn abort() -> ! {
+    loop {
+        unsafe { riscv::asm::ebreak() }
+    }
+}
+
+#[cfg(all(any(target_arch = "riscv32", target_arch = "riscv64"), feature = "riscv-wait-nop"))]
+#[inline]
+/// Prevent next `wait_for_interrupt` from sleeping, wake up other harts if needed.
+/// This particular implementation does nothing, since `wait_for_interrupt` never sleeps
+pub(crate) unsafe fn signal_event_ready() {}
+
+#[cfg(all(any(target_arch = "riscv32", target_arch = "riscv64"), feature = "riscv-wait-nop"))]
+#[inline]
+/// Wait for an interrupt or until notified by other hart via `signal_task_ready`
+/// This particular implementation does nothing
+pub(crate) unsafe fn wait_for_event() {}
+
+#[cfg(all(any(target_arch = "riscv32", target_arch = "riscv64"), feature = "riscv-wait-extern"))]
+extern "C" {
+    /// Prevent next `wait_for_interrupt` from sleeping, wake up other harts if needed.
+    /// User is expected to provide an actual implementation, like the one shown below.
+    ///
+    /// #[no_mangle]
+    /// pub extern "C" fn signal_event_ready() {
+    ///     unimplemented!();
+    /// }
+    pub(crate) fn signal_event_ready();
+
+    /// Wait for an interrupt or until notified by other hart via `signal_task_ready`
+    /// User is expected to provide an actual implementation, like the one shown below.
+    ///
+    /// #[no_mangle]
+    /// pub extern "C" fn wait_for_event() {
+    ///     unimplemented!();
+    /// }
+    pub(crate) fn wait_for_event();
+}
+
+#[cfg(all(any(target_arch = "riscv32", target_arch = "riscv64"), feature = "riscv-wait-wfi-single-hart"))]
+static mut TASK_READY: bool = false;
+
+#[cfg(all(any(target_arch = "riscv32", target_arch = "riscv64"), feature = "riscv-wait-wfi-single-hart"))]
+#[inline]
+/// Prevent next `wait_for_interrupt` from sleeping, wake up other harts if needed.
+/// This particular implementation prevents `wait_for_interrupt` from sleeping by setting
+/// a global mutable flag
+pub(crate) unsafe fn signal_event_ready() {
+    TASK_READY = true;
+}
+
+#[cfg(all(any(target_arch = "riscv32", target_arch = "riscv64"), feature = "riscv-wait-wfi-single-hart"))]
+#[inline]
+/// Wait for an interrupt or until notified by other hart via `signal_task_ready`
+/// This particular implementation decides whether to sleep or not by checking
+/// a global mutable flag that's set by `signal_task_ready`
+pub(crate) unsafe fn wait_for_event() {
+    if !TASK_READY {
+        riscv::asm::wfi();
+    }
+    TASK_READY = false;
+}
+
+/// Maximum number of tasks (TODO this could be user configurable)
+type NTASKS = typenum::consts::U8;

async-cortex-m/src/alloc.rs renamed to async-embedded/src/alloc.rs

@@ -6,8 +6,6 @@ use core::{
     task::{Context, Poll},
 };
 
-use cortex_m::asm;
-
 use crate::executor;
 
 /// Drives the future `f` to completion
@@ -43,7 +41,7 @@ pub async fn r#yield() {
                 self.yielded = true;
                 // wake ourselves
                 cx.waker().wake_by_ref();
-                asm::sev();
+                unsafe { crate::signal_event_ready(); }
                 Poll::Pending
             }
         }

async-cortex-m/src/executor.rs renamed to async-embedded/src/executor.rs

@@ -12,7 +12,6 @@ use core::{
     task::{Context, Poll},
 };
 
-use cortex_m::asm;
 use generic_array::{typenum::Unsigned, GenericArray};
 
 use super::waker_set::WakerSet;
@@ -137,7 +136,7 @@ impl<T> Channel<T> {
                 self.read.set(read.wrapping_add(1));
                 // notify a sender
                 self.send_wakers.notify_one();
-                asm::sev();
+                crate::signal_event_ready();
                 Some(val)
             } else {
                 // empty
@@ -162,7 +161,7 @@ impl<T> Channel<T> {
                 self.write.set(write.wrapping_add(1));
                 // notify a receiver
                 self.recv_wakers.notify_one();
-                asm::sev();
+                crate::signal_event_ready();
                 Ok(())
             } else {
                 // full