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Zero-length submodule name breaks things #1209

@tpwrules

Description

@tpwrules
Contributor

The following design:

from amaranth import *
from amaranth.back import verilog

class Bar(Elaboratable):
    def elaborate(self, platform):
        m = Module()
        m.d.sync += Signal().eq(1)
        return m

class Foo(Elaboratable):
    def elaborate(self, platform):
        m = Module()
        m.submodules[""] = Bar()
        return m

print(verilog.convert(Foo(), ports=[]))

gives the following exception:

Traceback (most recent call last):
  File "~/test.py", line 16, in <module>
    print(verilog.convert(Foo(), ports=[]))
  File "~/venv/lib/python3.10/site-packages/amaranth/back/verilog.py", line 61, in convert
    verilog_text, name_map = convert_fragment(fragment, ports, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs, **kwargs)
  File "~/venv/lib/python3.10/site-packages/amaranth/back/verilog.py", line 39, in convert_fragment
    rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
  File "~/venv/lib/python3.10/site-packages/amaranth/back/rtlil.py", line 1029, in convert_fragment
    empty_checker=empty_checker).emit()
  File "~/venv/lib/python3.10/site-packages/amaranth/back/rtlil.py", line 308, in emit
    self.emit_submodules()
  File "~/venv/lib/python3.10/site-packages/amaranth/back/rtlil.py", line 516, in emit_submodules
    self.builder.cell(f"\\{dotted_name}", submodule.name[-1], ports={
  File "~/venv/lib/python3.10/site-packages/amaranth/back/rtlil.py", line 166, in cell
    name = self._make_name(name, local=False)
  File "~/venv/lib/python3.10/site-packages/amaranth/back/rtlil.py", line 67, in _make_name
    elif not local and name[0] not in "\\$":
IndexError: string index out of range

I suggest that m.submodules[""] = ... have the same behavior as m.submodules += .... While it would be silly to directly write the former, it might arise from programmatic name generation, and should either work properly or immediately throw an error.

Activity

added this to the 0.5 milestone on Mar 22, 2024
tpwrules

tpwrules commented on Mar 23, 2024

@tpwrules
ContributorAuthor

Upon further consideration it's probably best to reject "" as an invalid name rather than try to do something magic with it.

whitequark

whitequark commented on Mar 24, 2024

@whitequark
Member

I suggest that m.submodules[""] = ... have the same behavior as m.submodules += .... While it would be silly to directly write the former, it might arise from programmatic name generation, and should either work properly or immediately throw an error.

I was actually thinking that this proposal seems OK. In fact, if you do m.submodules += they become "unnamed" and this is already surfaced in several places in the UI (like in error messages).

tpwrules

tpwrules commented on Mar 24, 2024

@tpwrules
ContributorAuthor

The specific situation I had in mind was that if you do m.submodules[x] = foo, then bar = m.submodules[x], this cannot work if x == "".

I'm fine with the concept of unnamed modules, but if you accidentally make x == "", then having the above break might be confusing. It does seem unlikely though.

whitequark

whitequark commented on Mar 24, 2024

@whitequark
Member

That's a good point, I forgot m.submodules[x] (reading) is a thing.

added a commit that references this issue on Jun 10, 2024
182330f
added a commit that references this issue on Jun 10, 2024
0140fe2
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        Zero-length submodule name breaks things · Issue #1209 · amaranth-lang/amaranth