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[WIP] Converting Yosys to Submodule

buildBuild systemBuild system

external_libs

lang-cppC/C++ codeC/C++ code

lang-hdlHardware Description Language (Verilog/VHDL)Hardware Description Language (Verilog/VHDL)

lang-makeCMake/Make codeCMake/Make code

lang-perlPerl codePerl code

lang-pythonPython codePython code

lang-shellShell scripts (bash etc.)Shell scripts (bash etc.)

Parmys

Status: Draft (not ready).

verilog-to-routing/vtr-verilog-to-routingnumber 3156

#3156 In verilog-to-routing/vtr-verilog-to-routing;

· loglav03 opened on Jun 20, 2025

[WIP] System Verilog Testing #3

external_libs

infraProject InfrastructureProject Infrastructure

lang-makeCMake/Make codeCMake/Make code

lang-pythonPython codePython code

Status: Draft (not ready).

verilog-to-routing/vtr-verilog-to-routingnumber 3114

#3114 In verilog-to-routing/vtr-verilog-to-routing;

· loglav03 opened on Jun 5, 2025

Logan Lavigne: WIP PR to compare yosys-upgrade testing

tests

Status: Draft (not ready).

verilog-to-routing/vtr-verilog-to-routingnumber 3089

#3089 In verilog-to-routing/vtr-verilog-to-routing;

· loglav03 opened on May 27, 2025