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Do not make models with no pin-to-pin relations constant generators #2058

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@mkurc-ant mkurc-ant commented Jun 9, 2022

Description

Currently for models with no pin-to-pin relations defined VPR assumes that their outputs become constant generators even though such models have inputs and they are connected to active logic.

This PR makes VPR stop implying that.

Related Issue

Motivation and Context

Generic blackbox support

How Has This Been Tested?

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Not sure though how breaking the change is. Probably a discussion is needed.

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

…nstant generators.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Not quite sure why the code change is as structured; needs a comment. Also, some tests are failing, so there seems to be some issue.

@@ -471,7 +471,7 @@ int mark_undriven_primitive_outputs_as_constant(AtomNetlist& netlist, int verbos
}
}

if (!has_connected_inputs) {
if (!has_connected_inputs && !upstream_ports.empty()) {
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This needs a comment explaining what !upstream_ports.empty() indicates (why is this not a constant generator if none of its inputs are connected to anything?). An example would be useful.

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Wouldn't a black box still have some inputs of the atom connected (so upstream_ports wouldn't necessarily be empty)? I am likely missing the point, but that means a comment with an example is needed I think.

@vaughnbetz
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@kmurray : this is a very short PR that would be good for you to take a look at as it's about timing analysis / graph.

@mkurc-ant
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@vaughnbetz @kmurray Indeed I see that the change I've made is breaking. Basically what I wanted to achieve is to make VPR not consider output of black-box models as constant sources. This is needed (at least for now) for FPGA interchange where we do not have (currently) pin-to-pin relations defined. With the current VPR we see that all cell outputs are considered constants which makes the placer ignore all nets hence it hangs in an infinite loop. I thought that this change might be beneficial for VPR in general as it makes blackbox models more usable.

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@mkurc-ant : not quite sure how to proceed with this one. If you'd like to discuss it, it would be good to put on the Thursday meeting agenda. Since it's breaking it seems we can't put it back in its current form.

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