-
Notifications
You must be signed in to change notification settings - Fork 418
Pull requests: verilog-to-routing/vtr-verilog-to-routing
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
Converter from rr_nodes to RRGraph object
docs
Documentation
infra
Project Infrastructure
lang-cpp
C/C++ code
lang-python
Python code
libvtrutil
scripts
Utility & Infrastructure scripts
tests
VPR
VPR FPGA Placement & Routing Tool
VTR Flow
VTR Design Flow (scripts/benchmarks/architectures)
#1048
opened Nov 15, 2019 by
tangxifan
Loading…
2 of 7 tasks
[CI] Added System Verilog Regression Tests to GitHub Runners
external_libs
infra
Project Infrastructure
lang-make
CMake/Make code
lang-python
Python code
#2885
opened Feb 7, 2025 by
AlexandreSinger
Loading…
Upgrade the Yosys+Odin-II Front-end
Odin
Odin II Logic Synthesis Tool: Unsorted item
Yosys+Odin-II
The Yosys+Odin-II synthesizer: the Yosys coarse-grained Tcl script and Odin-II partial mapping flow
#2148
opened Aug 29, 2022 by
sdamghan
Loading…
2 of 7 tasks
[Arch] Added Artix-7-like Devices on the Xilinx 7 Series Capture
#3139
opened Jun 15, 2025 by
AlexandreSinger
Loading…
fixed sdc file copy and parmys abs path to temp folder issue
lang-python
Python code
#2427
opened Nov 2, 2023 by
WhiteNinjaZ
Loading…
1 of 3 tasks
[WIP] Router Lookahead Profiler
build
Build system
external_libs
infra
Project Infrastructure
lang-cpp
C/C++ code
lang-make
CMake/Make code
lang-python
Python code
scripts
Utility & Infrastructure scripts
VPR
VPR FPGA Placement & Routing Tool
Fix bug in which all non-chain luts are considered length-1 chains.
VPR
VPR FPGA Placement & Routing Tool
#2363
opened Aug 8, 2023 by
KA7E
Loading…
7 tasks
Fixed Fc values for designs with different horizontal and vertical channel widths
VPR
VPR FPGA Placement & Routing Tool
#1822
opened Aug 9, 2021 by
bheiner14
Loading…
1 of 7 tasks
[Place] Centriod Initial Placement
lang-cpp
C/C++ code
libarchfpga
Library for handling FPGA Architecture descriptions
VPR
VPR FPGA Placement & Routing Tool
#3018
opened May 1, 2025 by
amin1377
Loading…
Support route constraint.
build
Build system
external_libs
lang-make
CMake/Make code
libarchfpga
Library for handling FPGA Architecture descriptions
libvtrutil
VPR
VPR FPGA Placement & Routing Tool
#2233
opened Jan 26, 2023 by
Tulong4Dev
Loading…
2 of 7 tasks
generate_tech_xml_files.sh
lang-python
Python code
lang-shell
Shell scripts (bash etc.)
#2426
opened Nov 2, 2023 by
zsjiang99
Loading…
1 of 7 tasks
FPGA interchange: add RR graph generation
external_libs
libarchfpga
Library for handling FPGA Architecture descriptions
VPR
VPR FPGA Placement & Routing Tool
#1999
opened Mar 16, 2022 by
acomodi
Loading…
1 of 7 tasks
Congestion Aware Placement
lang-cpp
C/C++ code
VPR
VPR FPGA Placement & Routing Tool
#2672
opened Aug 1, 2024 by
behzadmehmood-rs
•
Draft
7 tasks
Display more helpful error message when parsing a BLIF file that cont…
lang-cpp
C/C++ code
VPR
VPR FPGA Placement & Routing Tool
#340
opened May 6, 2018 by
benreynwar
Loading…
7 tasks
Improving Unrelated Clustering Feature in VPR
VPR
VPR FPGA Placement & Routing Tool
#2237
opened Feb 3, 2023 by
kimiatkh
Loading…
2 tasks
Do not make models with no pin-to-pin relations constant generators
VPR
VPR FPGA Placement & Routing Tool
#2058
opened Jun 9, 2022 by
mkurc-ant
Loading…
7 tasks
Router exit condition
lang-cpp
C/C++ code
VPR
VPR FPGA Placement & Routing Tool
#542
opened Apr 22, 2019 by
rfungquicklogic
Loading…
3 of 7 tasks
[Arch] Added Zero ASIC's Z1000 eFPGA Architecture
build
Build system
infra
Project Infrastructure
lang-make
CMake/Make code
lang-python
Python code
#3158
opened Jun 21, 2025 by
AlexandreSinger
Loading…
[AP][Solver] Per-Connection Timing Optimization
lang-cpp
C/C++ code
VPR
VPR FPGA Placement & Routing Tool
#3155
opened Jun 20, 2025 by
AlexandreSinger
Loading…
[NetlistWriter] Fixed Tcq SDF Writing for BlackBoxs
lang-cpp
C/C++ code
VPR
VPR FPGA Placement & Routing Tool
#3142
opened Jun 16, 2025 by
AlexandreSinger
Loading…
Previous Next
ProTip!
Adding no:label will show everything without a label.