Files

yosys

fpga: fixed a problem with logging into project.py

Nov 4, 2020

257594a · Nov 4, 2020

Name		Name	Last commit message	Last commit date
parent directory ..
Makefile		Makefile	examples/Makefile was split and distributed in simpler Makefiles	Oct 20, 2020
README.md		README.md	Updated examples/yosys	Sep 28, 2020
ise.py		ise.py	fpga: fixed a problem with logging into project.py	Nov 4, 2020
vivado.py		vivado.py	fpga: fixed a problem with logging into project.py	Nov 4, 2020
yosys.py		yosys.py	fpga: fixed a problem with logging into project.py	Nov 4, 2020

README.md

Yosys examples

Yosys synthesis

Verilog project: python3 yosys.py
VHDL project: python3 yosys.py --lang vhdl

Yosys using ISE as backend

Bitstream generation:

Verilog project: python3 ise.py
VHDL project: python3 ise.py --lang vhdl

Spartan-6 FPGA LX9 MicroBoard programming:

Verilog project: python3 ise.py --action transfer
VHDL project: python3 ise.py --lang vhdl --action transfer

Yosys using Vivado as backend

Bitstream generation:

Verilog project: python3 vivado.py
VHDL project: python3 vivado.py --lang vhdl

Zybo programming:

Verilog project: python3 vivado.py --action transfer
VHDL project: python3 vivado.py --lang vhdl --action transfer