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types.h
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// SPDX-License-Identifier: BSD-3-Clause
// Copyright (c) 2009-2024, Intel Corporation
// written by Roman Dementiev
//
#ifndef CPUCounters_TYPES_H
#define CPUCounters_TYPES_H
/*! \file types.h
\brief Internal type and constant definitions
*/
#undef PCM_DEBUG
#ifndef KERNEL
#include <iostream>
#include <istream>
#include <sstream>
#include <iomanip>
#include <string.h>
#include <assert.h>
#include <limits>
#ifdef _MSC_VER
#include <windows.h>
#include <intrin.h>
#endif
#endif // #ifndef KERNEL
namespace pcm {
typedef unsigned long long uint64;
typedef signed long long int64;
typedef unsigned int uint32;
typedef signed int int32;
#define PCM_ULIMIT_RECOMMENDATION ("try executing 'ulimit -n 1000000' to increase the limit on the number of open files.\n")
/*
MSR addresses from
"Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
System Programming Guide, Part 2", Appendix A "PERFORMANCE-MONITORING EVENTS"
*/
constexpr auto INST_RETIRED_ADDR = 0x309;
constexpr auto CPU_CLK_UNHALTED_THREAD_ADDR = 0x30A;
constexpr auto CPU_CLK_UNHALTED_REF_ADDR = 0x30B;
constexpr auto TOPDOWN_SLOTS_ADDR = 0x30C;
constexpr auto PERF_METRICS_ADDR = 0x329;
constexpr auto IA32_CR_PERF_GLOBAL_CTRL = 0x38F;
constexpr auto IA32_CR_FIXED_CTR_CTRL = 0x38D;
constexpr auto IA32_PERFEVTSEL0_ADDR = 0x186;
constexpr auto IA32_PERFEVTSEL1_ADDR = IA32_PERFEVTSEL0_ADDR + 1;
constexpr auto IA32_PERFEVTSEL2_ADDR = IA32_PERFEVTSEL0_ADDR + 2;
constexpr auto IA32_PERFEVTSEL3_ADDR = IA32_PERFEVTSEL0_ADDR + 3;
constexpr auto IA32_PERF_GLOBAL_STATUS = 0x38E;
constexpr auto IA32_PERF_GLOBAL_OVF_CTRL = 0x390;
constexpr auto IA32_PEBS_ENABLE_ADDR = 0x3F1;
constexpr auto PERF_MAX_FIXED_COUNTERS = 3;
constexpr auto PERF_MAX_CUSTOM_COUNTERS = 8;
constexpr auto PERF_TOPDOWN_COUNTERS_L1 = 5;
constexpr auto PERF_TOPDOWN_COUNTERS = PERF_TOPDOWN_COUNTERS_L1 + 4;
constexpr auto PERF_MAX_COUNTERS = PERF_MAX_FIXED_COUNTERS + PERF_MAX_CUSTOM_COUNTERS + PERF_TOPDOWN_COUNTERS;
constexpr auto IA32_DEBUGCTL = 0x1D9;
constexpr auto IA32_PMC0 = 0xC1;
constexpr auto IA32_PMC1 = IA32_PMC0 + 1;
constexpr auto IA32_PMC2 = IA32_PMC0 + 2;
constexpr auto IA32_PMC3 = IA32_PMC0 + 3;
constexpr auto MSR_OFFCORE_RSP0 = 0x1A6;
constexpr auto MSR_OFFCORE_RSP1 = 0x1A7;
constexpr auto MSR_LOAD_LATENCY = 0x3F6;
constexpr auto MSR_FRONTEND = 0x3F7;
/* From Table B-5. of the above mentioned document */
constexpr auto PLATFORM_INFO_ADDR = 0xCE;
constexpr auto IA32_TIME_STAMP_COUNTER = 0x10;
// Event IDs
// Nehalem/Westmere on-core events
constexpr auto MEM_LOAD_RETIRED_L3_MISS_EVTNR = 0xCB;
constexpr auto MEM_LOAD_RETIRED_L3_MISS_UMASK = 0x10;
constexpr auto MEM_LOAD_RETIRED_L3_UNSHAREDHIT_EVTNR = 0xCB;
constexpr auto MEM_LOAD_RETIRED_L3_UNSHAREDHIT_UMASK = 0x04;
constexpr auto MEM_LOAD_RETIRED_L2_HITM_EVTNR = 0xCB;
constexpr auto MEM_LOAD_RETIRED_L2_HITM_UMASK = 0x08;
constexpr auto MEM_LOAD_RETIRED_L2_HIT_EVTNR = 0xCB;
constexpr auto MEM_LOAD_RETIRED_L2_HIT_UMASK = 0x02;
// Sandy Bridge on-core events
constexpr auto MEM_LOAD_UOPS_MISC_RETIRED_LLC_MISS_EVTNR = 0xD4;
constexpr auto MEM_LOAD_UOPS_MISC_RETIRED_LLC_MISS_UMASK = 0x02;
constexpr auto MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_NONE_EVTNR = 0xD2;
constexpr auto MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_NONE_UMASK = 0x08;
constexpr auto MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_HITM_EVTNR = 0xD2;
constexpr auto MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_HITM_UMASK = 0x04;
constexpr auto MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_EVTNR = 0xD2;
constexpr auto MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_UMASK = 0x07;
constexpr auto MEM_LOAD_UOPS_RETIRED_L2_HIT_EVTNR = 0xD1;
constexpr auto MEM_LOAD_UOPS_RETIRED_L2_HIT_UMASK = 0x02;
// Haswell on-core events
constexpr auto HSX_L2_RQSTS_MISS_EVTNR = 0x24;
constexpr auto HSX_L2_RQSTS_MISS_UMASK = 0x3f;
constexpr auto HSX_L2_RQSTS_REFERENCES_EVTNR = 0x24;
constexpr auto HSX_L2_RQSTS_REFERENCES_UMASK = 0xff;
// Skylake on-core events
#define SKL_MEM_LOAD_RETIRED_L3_MISS_EVTNR (0xD1)
#define SKL_MEM_LOAD_RETIRED_L3_MISS_UMASK (0x20)
#define SKL_MEM_LOAD_RETIRED_L3_HIT_EVTNR (0xD1)
#define SKL_MEM_LOAD_RETIRED_L3_HIT_UMASK (0x04)
#define SKL_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xD1)
#define SKL_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x10)
#define SKL_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xD1)
#define SKL_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x02)
// Crestmont on-core events
constexpr auto CMT_MEM_LOAD_RETIRED_L2_MISS_EVTNR = 0xD1;
constexpr auto CMT_MEM_LOAD_RETIRED_L2_MISS_UMASK = 0x80;
constexpr auto CMT_MEM_LOAD_RETIRED_L2_HIT_EVTNR = 0xD1;
constexpr auto CMT_MEM_LOAD_RETIRED_L2_HIT_UMASK = 0x02;
// architectural on-core events
constexpr auto ARCH_LLC_REFERENCE_EVTNR = 0x2E;
constexpr auto ARCH_LLC_REFERENCE_UMASK = 0x4F;
constexpr auto ARCH_LLC_MISS_EVTNR = 0x2E;
constexpr auto ARCH_LLC_MISS_UMASK = 0x41;
// Atom on-core events
constexpr auto ATOM_MEM_LOAD_RETIRED_L2_HIT_EVTNR = 0xCB;
constexpr auto ATOM_MEM_LOAD_RETIRED_L2_HIT_UMASK = 0x01;
constexpr auto ATOM_MEM_LOAD_RETIRED_L2_MISS_EVTNR = 0xCB;
constexpr auto ATOM_MEM_LOAD_RETIRED_L2_MISS_UMASK = 0x02;
// Offcore response events
constexpr auto OFFCORE_RESPONSE_0_EVTNR = 0xB7;
constexpr auto OFFCORE_RESPONSE_1_EVTNR = 0xBB;
constexpr auto GLC_OFFCORE_RESPONSE_0_EVTNR = 0x2A;
constexpr auto GLC_OFFCORE_RESPONSE_1_EVTNR = 0x2B;
constexpr auto OFFCORE_RESPONSE_0_UMASK = 1;
constexpr auto OFFCORE_RESPONSE_1_UMASK = 1;
constexpr auto LOAD_LATENCY_EVTNR = 0xcd;
constexpr auto LOAD_LATENCY_UMASK = 0x01;
constexpr auto FRONTEND_EVTNR = 0xC6;
constexpr auto FRONTEND_UMASK = 0x01;
/*
For Nehalem(-EP) processors from Intel(r) 64 and IA-32 Architectures Software Developer's Manual
*/
// Uncore msrs
constexpr auto MSR_UNCORE_PERF_GLOBAL_CTRL_ADDR = 0x391;
constexpr auto MSR_UNCORE_PERFEVTSEL0_ADDR = 0x3C0;
constexpr auto MSR_UNCORE_PERFEVTSEL1_ADDR = MSR_UNCORE_PERFEVTSEL0_ADDR + 1;
constexpr auto MSR_UNCORE_PERFEVTSEL2_ADDR = MSR_UNCORE_PERFEVTSEL0_ADDR + 2;
constexpr auto MSR_UNCORE_PERFEVTSEL3_ADDR = MSR_UNCORE_PERFEVTSEL0_ADDR + 3;
constexpr auto MSR_UNCORE_PERFEVTSEL4_ADDR = MSR_UNCORE_PERFEVTSEL0_ADDR + 4;
constexpr auto MSR_UNCORE_PERFEVTSEL5_ADDR = MSR_UNCORE_PERFEVTSEL0_ADDR + 5;
constexpr auto MSR_UNCORE_PERFEVTSEL6_ADDR = MSR_UNCORE_PERFEVTSEL0_ADDR + 6;
constexpr auto MSR_UNCORE_PERFEVTSEL7_ADDR = MSR_UNCORE_PERFEVTSEL0_ADDR + 7;
constexpr auto MSR_UNCORE_PMC0 = 0x3B0;
constexpr auto MSR_UNCORE_PMC1 = MSR_UNCORE_PMC0 + 1;
constexpr auto MSR_UNCORE_PMC2 = MSR_UNCORE_PMC0 + 2;
constexpr auto MSR_UNCORE_PMC3 = MSR_UNCORE_PMC0 + 3;
constexpr auto MSR_UNCORE_PMC4 = MSR_UNCORE_PMC0 + 4;
constexpr auto MSR_UNCORE_PMC5 = MSR_UNCORE_PMC0 + 5;
constexpr auto MSR_UNCORE_PMC6 = MSR_UNCORE_PMC0 + 6;
constexpr auto MSR_UNCORE_PMC7 = MSR_UNCORE_PMC0 + 7;
// Uncore event IDs
constexpr auto UNC_QMC_WRITES_FULL_ANY_EVTNR = 0x2F;
constexpr auto UNC_QMC_WRITES_FULL_ANY_UMASK = 0x07;
constexpr auto UNC_QMC_NORMAL_READS_ANY_EVTNR = 0x2C;
constexpr auto UNC_QMC_NORMAL_READS_ANY_UMASK = 0x07;
constexpr auto UNC_QHL_REQUESTS_EVTNR = 0x20;
constexpr auto UNC_QHL_REQUESTS_IOH_READS_UMASK = 0x01;
constexpr auto UNC_QHL_REQUESTS_IOH_WRITES_UMASK = 0x02;
constexpr auto UNC_QHL_REQUESTS_REMOTE_READS_UMASK = 0x04;
constexpr auto UNC_QHL_REQUESTS_REMOTE_WRITES_UMASK = 0x08;
constexpr auto UNC_QHL_REQUESTS_LOCAL_READS_UMASK = 0x10;
constexpr auto UNC_QHL_REQUESTS_LOCAL_WRITES_UMASK = 0x20;
/*
From "Intel(r) Xeon(r) Processor 7500 Series Uncore Programming Guide"
*/
// Beckton uncore event IDs
constexpr auto U_MSR_PMON_GLOBAL_CTL = 0x0C00;
constexpr auto MB0_MSR_PERF_GLOBAL_CTL = 0x0CA0;
constexpr auto MB0_MSR_PMU_CNT_0 = 0x0CB1;
constexpr auto MB0_MSR_PMU_CNT_CTL_0 = 0x0CB0;
constexpr auto MB0_MSR_PMU_CNT_1 = 0x0CB3;
constexpr auto MB0_MSR_PMU_CNT_CTL_1 = 0x0CB2;
constexpr auto MB0_MSR_PMU_ZDP_CTL_FVC = 0x0CAB;
constexpr auto MB1_MSR_PERF_GLOBAL_CTL = 0x0CE0;
constexpr auto MB1_MSR_PMU_CNT_0 = 0x0CF1;
constexpr auto MB1_MSR_PMU_CNT_CTL_0 = 0x0CF0;
constexpr auto MB1_MSR_PMU_CNT_1 = 0x0CF3;
constexpr auto MB1_MSR_PMU_CNT_CTL_1 = 0x0CF2;
constexpr auto MB1_MSR_PMU_ZDP_CTL_FVC = 0x0CEB;
constexpr auto BB0_MSR_PERF_GLOBAL_CTL = 0x0C20;
constexpr auto BB0_MSR_PERF_CNT_1 = 0x0C33;
constexpr auto BB0_MSR_PERF_CNT_CTL_1 = 0x0C32;
constexpr auto BB1_MSR_PERF_GLOBAL_CTL = 0x0C60;
constexpr auto BB1_MSR_PERF_CNT_1 = 0x0C73;
constexpr auto BB1_MSR_PERF_CNT_CTL_1 = 0x0C72;
constexpr auto R_MSR_PMON_CTL0 = 0x0E10;
constexpr auto R_MSR_PMON_CTR0 = 0x0E11;
constexpr auto R_MSR_PMON_CTL1 = 0x0E12;
constexpr auto R_MSR_PMON_CTR1 = 0x0E13;
constexpr auto R_MSR_PMON_CTL2 = 0x0E14;
constexpr auto R_MSR_PMON_CTR2 = 0x0E15;
constexpr auto R_MSR_PMON_CTL3 = 0x0E16;
constexpr auto R_MSR_PMON_CTR3 = 0x0E17;
constexpr auto R_MSR_PMON_CTL4 = 0x0E18;
constexpr auto R_MSR_PMON_CTR4 = 0x0E19;
constexpr auto R_MSR_PMON_CTL5 = 0x0E1A;
constexpr auto R_MSR_PMON_CTR5 = 0x0E1B;
constexpr auto R_MSR_PMON_CTL6 = 0x0E1C;
constexpr auto R_MSR_PMON_CTR6 = 0x0E1D;
constexpr auto R_MSR_PMON_CTL7 = 0x0E1E;
constexpr auto R_MSR_PMON_CTR7 = 0x0E1F;
constexpr auto R_MSR_PMON_CTL8 = 0x0E30;
constexpr auto R_MSR_PMON_CTR8 = 0x0E31;
constexpr auto R_MSR_PMON_CTL9 = 0x0E32;
constexpr auto R_MSR_PMON_CTR9 = 0x0E33;
constexpr auto R_MSR_PMON_CTL10 = 0x0E34;
constexpr auto R_MSR_PMON_CTR10 = 0x0E35;
constexpr auto R_MSR_PMON_CTL11 = 0x0E36;
constexpr auto R_MSR_PMON_CTR11 = 0x0E37;
constexpr auto R_MSR_PMON_CTL12 = 0x0E38;
constexpr auto R_MSR_PMON_CTR12 = 0x0E39;
constexpr auto R_MSR_PMON_CTL13 = 0x0E3A;
constexpr auto R_MSR_PMON_CTR13 = 0x0E3B;
constexpr auto R_MSR_PMON_CTL14 = 0x0E3C;
constexpr auto R_MSR_PMON_CTR14 = 0x0E3D;
constexpr auto R_MSR_PMON_CTL15 = 0x0E3E;
constexpr auto R_MSR_PMON_CTR15 = 0x0E3F;
constexpr auto R_MSR_PORT0_IPERF_CFG0 = 0x0E04;
constexpr auto R_MSR_PORT1_IPERF_CFG0 = 0x0E05;
constexpr auto R_MSR_PORT2_IPERF_CFG0 = 0x0E06;
constexpr auto R_MSR_PORT3_IPERF_CFG0 = 0x0E07;
constexpr auto R_MSR_PORT4_IPERF_CFG0 = 0x0E08;
constexpr auto R_MSR_PORT5_IPERF_CFG0 = 0x0E09;
constexpr auto R_MSR_PORT6_IPERF_CFG0 = 0x0E0A;
constexpr auto R_MSR_PORT7_IPERF_CFG0 = 0x0E0B;
constexpr auto R_MSR_PORT0_IPERF_CFG1 = 0x0E24;
constexpr auto R_MSR_PORT1_IPERF_CFG1 = 0x0E25;
constexpr auto R_MSR_PORT2_IPERF_CFG1 = 0x0E26;
constexpr auto R_MSR_PORT3_IPERF_CFG1 = 0x0E27;
constexpr auto R_MSR_PORT4_IPERF_CFG1 = 0x0E28;
constexpr auto R_MSR_PORT5_IPERF_CFG1 = 0x0E29;
constexpr auto R_MSR_PORT6_IPERF_CFG1 = 0x0E2A;
constexpr auto R_MSR_PORT7_IPERF_CFG1 = 0x0E2B;
constexpr auto R_MSR_PMON_GLOBAL_CTL_7_0 = 0x0E00;
constexpr auto R_MSR_PMON_GLOBAL_CTL_15_8 = 0x0E20;
constexpr auto W_MSR_PMON_GLOBAL_CTL = 0xC80;
constexpr auto W_MSR_PMON_FIXED_CTR_CTL = 0x395;
constexpr auto W_MSR_PMON_FIXED_CTR = 0x394;
/*
* Platform QoS MSRs
*/
constexpr auto IA32_PQR_ASSOC = 0xc8f;
constexpr auto IA32_QM_EVTSEL = 0xc8d;
constexpr auto IA32_QM_CTR = 0xc8e;
#ifndef KERNEL
constexpr auto PCM_INVALID_QOS_MONITORING_DATA = (std::numeric_limits<uint64>::max)();
#endif
/* \brief Event Select Register format
According to
"Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
System Programming Guide, Part 2", Figure 30-6. Layout of IA32_PERFEVTSELx
MSRs Supporting Architectural Performance Monitoring Version 3
*/
struct EventSelectRegister
{
union
{
struct
{
uint64 event_select : 8;
uint64 umask : 8;
uint64 usr : 1;
uint64 os : 1;
uint64 edge : 1;
uint64 pin_control : 1;
uint64 apic_int : 1;
uint64 any_thread : 1;
uint64 enable : 1;
uint64 invert : 1;
uint64 cmask : 8;
uint64 in_tx : 1;
uint64 in_txcp : 1;
uint64 reservedX : 30;
} fields;
uint64 value;
};
EventSelectRegister() : value(0) {}
};
/* \brief Fixed Event Control Register format
According to
"Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
System Programming Guide, Part 2", Figure 30-7. Layout of
IA32_FIXED_CTR_CTRL MSR Supporting Architectural Performance Monitoring Version 3
*/
struct FixedEventControlRegister
{
union
{
struct
{
// CTR0
uint64 os0 : 1;
uint64 usr0 : 1;
uint64 any_thread0 : 1;
uint64 enable_pmi0 : 1;
// CTR1
uint64 os1 : 1;
uint64 usr1 : 1;
uint64 any_thread1 : 1;
uint64 enable_pmi1 : 1;
// CTR2
uint64 os2 : 1;
uint64 usr2 : 1;
uint64 any_thread2 : 1;
uint64 enable_pmi2 : 1;
// CTR3
uint64 os3 : 1;
uint64 usr3 : 1;
uint64 any_thread3 : 1;
uint64 enable_pmi3 : 1;
uint64 reserved1 : 48;
} fields;
uint64 value;
};
FixedEventControlRegister() : value(0) {}
};
#ifndef KERNEL
inline std::ostream & operator << (std::ostream & o, const FixedEventControlRegister & reg)
{
o << "os0\t\t" << reg.fields.os0 << "\n";
o << "usr0\t\t" << reg.fields.usr0 << "\n";
o << "any_thread0\t" << reg.fields.any_thread0 << "\n";
o << "enable_pmi0\t" << reg.fields.enable_pmi0 << "\n";
o << "os1\t\t" << reg.fields.os1 << "\n";
o << "usr1\t\t" << reg.fields.usr1 << "\n";
o << "any_thread1\t" << reg.fields.any_thread1 << "\n";
o << "enable_pmi10\t" << reg.fields.enable_pmi1 << "\n";
o << "os2\t\t" << reg.fields.os2 << "\n";
o << "usr2\t\t" << reg.fields.usr2 << "\n";
o << "any_thread2\t" << reg.fields.any_thread2 << "\n";
o << "enable_pmi2\t" << reg.fields.enable_pmi2 << "\n";
o << "reserved1\t" << reg.fields.reserved1 << "\n";
return o;
}
#endif // #ifndef KERNEL
// UNCORE COUNTER CONTROL
/* \brief Uncore Event Select Register Register format
According to
"Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
System Programming Guide, Part 2", Figure 30-20. Layout of MSR_UNCORE_PERFEVTSELx MSRs
*/
struct UncoreEventSelectRegister
{
union
{
struct
{
uint64 event_select : 8;
uint64 umask : 8;
uint64 reserved1 : 1;
uint64 occ_ctr_rst : 1;
uint64 edge : 1;
uint64 reserved2 : 1;
uint64 enable_pmi : 1;
uint64 reserved3 : 1;
uint64 enable : 1;
uint64 invert : 1;
uint64 cmask : 8;
uint64 reservedx : 32;
} fields;
uint64 value;
};
};
/* \brief Beckton Uncore PMU ZDP FVC Control Register format
From "Intel(r) Xeon(r) Processor 7500 Series Uncore Programming Guide"
Table 2-80. M_MSR_PMU_ZDP_CTL_FVC Register - Field Definitions
*/
struct BecktonUncorePMUZDPCTLFVCRegister
{
union
{
struct
{
uint64 fvid : 5;
uint64 bcmd : 3;
uint64 resp : 3;
uint64 evnt0 : 3;
uint64 evnt1 : 3;
uint64 evnt2 : 3;
uint64 evnt3 : 3;
uint64 pbox_init_err : 1;
} fields; // nehalem-ex version
struct
{
uint64 fvid : 6;
uint64 bcmd : 3;
uint64 resp : 3;
uint64 evnt0 : 3;
uint64 evnt1 : 3;
uint64 evnt2 : 3;
uint64 evnt3 : 3;
uint64 pbox_init_err : 1;
} fields_wsm; // westmere-ex version
uint64 value;
};
};
/* \brief Beckton Uncore PMU Counter Control Register format
From "Intel(r) Xeon(r) Processor 7500 Series Uncore Programming Guide"
Table 2-67. M_MSR_PMU_CNT_CTL{5-0} Register - Field Definitions
*/
struct BecktonUncorePMUCNTCTLRegister
{
union
{
struct
{
uint64 en : 1;
uint64 pmi_en : 1;
uint64 count_mode : 2;
uint64 storage_mode : 2;
uint64 wrap_mode : 1;
uint64 flag_mode : 1;
uint64 rsv1 : 1;
uint64 inc_sel : 5;
uint64 rsv2 : 5;
uint64 set_flag_sel : 3;
} fields;
uint64 value;
};
};
constexpr auto MSR_SMI_COUNT = 0x34;
/* \brief Sandy Bridge energy counters
*/
constexpr auto MSR_PKG_ENERGY_STATUS = 0x611;
constexpr auto MSR_SYS_ENERGY_STATUS = 0x64D;
constexpr auto MSR_RAPL_POWER_UNIT = 0x606;
constexpr auto MSR_PKG_POWER_INFO = 0x614;
constexpr auto PCM_INTEL_PCI_VENDOR_ID = 0x8086;
constexpr auto PCM_PCI_VENDOR_ID_OFFSET = 0;
// server PCICFG uncore counters
constexpr auto JKTIVT_MC0_CH0_REGISTER_DEV_ADDR = 16;
constexpr auto JKTIVT_MC0_CH1_REGISTER_DEV_ADDR = 16;
constexpr auto JKTIVT_MC0_CH2_REGISTER_DEV_ADDR = 16;
constexpr auto JKTIVT_MC0_CH3_REGISTER_DEV_ADDR = 16;
constexpr auto JKTIVT_MC0_CH0_REGISTER_FUNC_ADDR = 4;
constexpr auto JKTIVT_MC0_CH1_REGISTER_FUNC_ADDR = 5;
constexpr auto JKTIVT_MC0_CH2_REGISTER_FUNC_ADDR = 0;
constexpr auto JKTIVT_MC0_CH3_REGISTER_FUNC_ADDR = 1;
constexpr auto JKTIVT_MC1_CH0_REGISTER_DEV_ADDR = 30;
constexpr auto JKTIVT_MC1_CH1_REGISTER_DEV_ADDR = 30;
constexpr auto JKTIVT_MC1_CH2_REGISTER_DEV_ADDR = 30;
constexpr auto JKTIVT_MC1_CH3_REGISTER_DEV_ADDR = 30;
constexpr auto JKTIVT_MC1_CH0_REGISTER_FUNC_ADDR = 4;
constexpr auto JKTIVT_MC1_CH1_REGISTER_FUNC_ADDR = 5;
constexpr auto JKTIVT_MC1_CH2_REGISTER_FUNC_ADDR = 0;
constexpr auto JKTIVT_MC1_CH3_REGISTER_FUNC_ADDR = 1;
constexpr auto HSX_MC0_CH0_REGISTER_DEV_ADDR = 20;
constexpr auto HSX_MC0_CH1_REGISTER_DEV_ADDR = 20;
constexpr auto HSX_MC0_CH2_REGISTER_DEV_ADDR = 21;
constexpr auto HSX_MC0_CH3_REGISTER_DEV_ADDR = 21;
constexpr auto HSX_MC0_CH0_REGISTER_FUNC_ADDR = 0;
constexpr auto HSX_MC0_CH1_REGISTER_FUNC_ADDR = 1;
constexpr auto HSX_MC0_CH2_REGISTER_FUNC_ADDR = 0;
constexpr auto HSX_MC0_CH3_REGISTER_FUNC_ADDR = 1;
constexpr auto HSX_MC1_CH0_REGISTER_DEV_ADDR = 23;
constexpr auto HSX_MC1_CH1_REGISTER_DEV_ADDR = 23;
constexpr auto HSX_MC1_CH2_REGISTER_DEV_ADDR = 24;
constexpr auto HSX_MC1_CH3_REGISTER_DEV_ADDR = 24;
constexpr auto HSX_MC1_CH0_REGISTER_FUNC_ADDR = 0;
constexpr auto HSX_MC1_CH1_REGISTER_FUNC_ADDR = 1;
constexpr auto HSX_MC1_CH2_REGISTER_FUNC_ADDR = 0;
constexpr auto HSX_MC1_CH3_REGISTER_FUNC_ADDR = 1;
constexpr auto KNL_MC0_CH0_REGISTER_DEV_ADDR = 8;
constexpr auto KNL_MC0_CH1_REGISTER_DEV_ADDR = 8;
constexpr auto KNL_MC0_CH2_REGISTER_DEV_ADDR = 8;
constexpr auto KNL_MC0_CH0_REGISTER_FUNC_ADDR = 2;
constexpr auto KNL_MC0_CH1_REGISTER_FUNC_ADDR = 3;
constexpr auto KNL_MC0_CH2_REGISTER_FUNC_ADDR = 4;
constexpr auto SKX_MC0_CH0_REGISTER_DEV_ADDR = 10;
constexpr auto SKX_MC0_CH1_REGISTER_DEV_ADDR = 10;
constexpr auto SKX_MC0_CH2_REGISTER_DEV_ADDR = 11;
constexpr auto SKX_MC0_CH3_REGISTER_DEV_ADDR = -1; //Does not exist
constexpr auto SKX_MC0_CH0_REGISTER_FUNC_ADDR = 2;
constexpr auto SKX_MC0_CH1_REGISTER_FUNC_ADDR = 6;
constexpr auto SKX_MC0_CH2_REGISTER_FUNC_ADDR = 2;
constexpr auto SKX_MC0_CH3_REGISTER_FUNC_ADDR = -1; //Does not exist
constexpr auto SKX_MC1_CH0_REGISTER_DEV_ADDR = 12;
constexpr auto SKX_MC1_CH1_REGISTER_DEV_ADDR = 12;
constexpr auto SKX_MC1_CH2_REGISTER_DEV_ADDR = 13;
constexpr auto SKX_MC1_CH3_REGISTER_DEV_ADDR = -1; //Does not exist
constexpr auto SKX_MC1_CH0_REGISTER_FUNC_ADDR = 2;
constexpr auto SKX_MC1_CH1_REGISTER_FUNC_ADDR = 6;
constexpr auto SKX_MC1_CH2_REGISTER_FUNC_ADDR = 2;
constexpr auto SKX_MC1_CH3_REGISTER_FUNC_ADDR = -1; //Does not exist
constexpr auto SERVER_UBOX0_REGISTER_DEV_ADDR = 0;
constexpr auto SERVER_UBOX0_REGISTER_FUNC_ADDR = 1;
constexpr auto KNL_MC1_CH0_REGISTER_DEV_ADDR = 9;
constexpr auto KNL_MC1_CH1_REGISTER_DEV_ADDR = 9;
constexpr auto KNL_MC1_CH2_REGISTER_DEV_ADDR = 9;
constexpr auto KNL_MC1_CH0_REGISTER_FUNC_ADDR = 2;
constexpr auto KNL_MC1_CH1_REGISTER_FUNC_ADDR = 3;
constexpr auto KNL_MC1_CH2_REGISTER_FUNC_ADDR = 4;
constexpr auto KNL_EDC0_ECLK_REGISTER_DEV_ADDR = 24;
constexpr auto KNL_EDC0_ECLK_REGISTER_FUNC_ADDR = 2;
constexpr auto KNL_EDC1_ECLK_REGISTER_DEV_ADDR = 25;
constexpr auto KNL_EDC1_ECLK_REGISTER_FUNC_ADDR = 2;
constexpr auto KNL_EDC2_ECLK_REGISTER_DEV_ADDR = 26;
constexpr auto KNL_EDC2_ECLK_REGISTER_FUNC_ADDR = 2;
constexpr auto KNL_EDC3_ECLK_REGISTER_DEV_ADDR = 27;
constexpr auto KNL_EDC3_ECLK_REGISTER_FUNC_ADDR = 2;
constexpr auto KNL_EDC4_ECLK_REGISTER_DEV_ADDR = 28;
constexpr auto KNL_EDC4_ECLK_REGISTER_FUNC_ADDR = 2;
constexpr auto KNL_EDC5_ECLK_REGISTER_DEV_ADDR = 29;
constexpr auto KNL_EDC5_ECLK_REGISTER_FUNC_ADDR = 2;
constexpr auto KNL_EDC6_ECLK_REGISTER_DEV_ADDR = 30;
constexpr auto KNL_EDC6_ECLK_REGISTER_FUNC_ADDR = 2;
constexpr auto KNL_EDC7_ECLK_REGISTER_DEV_ADDR = 31;
constexpr auto KNL_EDC7_ECLK_REGISTER_FUNC_ADDR = 2;
constexpr auto HSX_HA0_REGISTER_DEV_ADDR = 18;
constexpr auto HSX_HA0_REGISTER_FUNC_ADDR = 1;
constexpr auto HSX_HA1_REGISTER_DEV_ADDR = 18;
constexpr auto HSX_HA1_REGISTER_FUNC_ADDR = 5;
constexpr auto XPF_HA_PCI_PMON_BOX_CTL_ADDR = 0xF4;
constexpr auto XPF_HA_PCI_PMON_CTL0_ADDR = 0xD8 + 4*0;
constexpr auto XPF_HA_PCI_PMON_CTL1_ADDR = 0xD8 + 4*1;
constexpr auto XPF_HA_PCI_PMON_CTL2_ADDR = 0xD8 + 4*2;
constexpr auto XPF_HA_PCI_PMON_CTL3_ADDR = 0xD8 + 4*3;
constexpr auto XPF_HA_PCI_PMON_CTR0_ADDR = 0xA0 + 8*0;
constexpr auto XPF_HA_PCI_PMON_CTR1_ADDR = 0xA0 + 8*1;
constexpr auto XPF_HA_PCI_PMON_CTR2_ADDR = 0xA0 + 8*2;
constexpr auto XPF_HA_PCI_PMON_CTR3_ADDR = 0xA0 + 8*3;
constexpr auto BHS_PCIE_GEN5_PCI_PMON_BOX_CTL_ADDR = 0x620;
constexpr auto BHS_PCIE_GEN5_PCI_PMON_CTL0_ADDR = 0x630;
constexpr auto BHS_PCIE_GEN5_PCI_PMON_CTR0_ADDR = 0x650;
/**
* XPF_ for Xeons: SNB, IVT, HSX, BDW, etc.
* KNX_ for Xeon Phi (Knights *) processors
*/
constexpr auto XPF_MC_CH_PCI_PMON_BOX_CTL_ADDR = 0x0F4;
constexpr auto KNX_MC_CH_PCI_PMON_BOX_CTL_ADDR = 0xB30;
constexpr auto KNX_EDC_CH_PCI_PMON_BOX_CTL_ADDR = 0xA30;
//! for Xeons
constexpr auto XPF_MC_CH_PCI_PMON_FIXED_CTL_ADDR = 0x0F0;
constexpr auto XPF_MC_CH_PCI_PMON_CTL3_ADDR = 0x0E4;
constexpr auto XPF_MC_CH_PCI_PMON_CTL2_ADDR = 0x0E0;
constexpr auto XPF_MC_CH_PCI_PMON_CTL1_ADDR = 0x0DC;
constexpr auto XPF_MC_CH_PCI_PMON_CTL0_ADDR = 0x0D8;
//! KNL IMC
constexpr auto KNX_MC_CH_PCI_PMON_FIXED_CTL_ADDR = 0xB44;
constexpr auto KNX_MC_CH_PCI_PMON_CTL3_ADDR = 0xB2C;
constexpr auto KNX_MC_CH_PCI_PMON_CTL2_ADDR = 0xB28;
constexpr auto KNX_MC_CH_PCI_PMON_CTL1_ADDR = 0xB24;
constexpr auto KNX_MC_CH_PCI_PMON_CTL0_ADDR = 0xB20;
//! KNL EDC ECLK
constexpr auto KNX_EDC_CH_PCI_PMON_FIXED_CTL_ADDR = 0xA44;
constexpr auto KNX_EDC_CH_PCI_PMON_CTL3_ADDR = 0xA2C;
constexpr auto KNX_EDC_CH_PCI_PMON_CTL2_ADDR = 0xA28;
constexpr auto KNX_EDC_CH_PCI_PMON_CTL1_ADDR = 0xA24;
constexpr auto KNX_EDC_CH_PCI_PMON_CTL0_ADDR = 0xA20;
constexpr auto KNX_EDC_ECLK_PMON_UNIT_CTL_REG = 0xA30;
//! for Xeons
constexpr auto XPF_MC_CH_PCI_PMON_FIXED_CTR_ADDR = 0x0D0;
constexpr auto XPF_MC_CH_PCI_PMON_CTR3_ADDR = 0x0B8;
constexpr auto XPF_MC_CH_PCI_PMON_CTR2_ADDR = 0x0B0;
constexpr auto XPF_MC_CH_PCI_PMON_CTR1_ADDR = 0x0A8;
constexpr auto XPF_MC_CH_PCI_PMON_CTR0_ADDR = 0x0A0;
//! for KNL IMC
constexpr auto KNX_MC_CH_PCI_PMON_FIXED_CTR_ADDR = 0xB3C;
constexpr auto KNX_MC_CH_PCI_PMON_CTR3_ADDR = 0xB18;
constexpr auto KNX_MC_CH_PCI_PMON_CTR2_ADDR = 0xB10;
constexpr auto KNX_MC_CH_PCI_PMON_CTR1_ADDR = 0xB08;
constexpr auto KNX_MC_CH_PCI_PMON_CTR0_ADDR = 0xB00;
//! for KNL EDC ECLK
constexpr auto KNX_EDC_CH_PCI_PMON_FIXED_CTR_ADDR = 0xA3C;
constexpr auto KNX_EDC_CH_PCI_PMON_CTR3_ADDR = 0xA18;
constexpr auto KNX_EDC_CH_PCI_PMON_CTR2_ADDR = 0xA10;
constexpr auto KNX_EDC_CH_PCI_PMON_CTR1_ADDR = 0xA08;
constexpr auto KNX_EDC_CH_PCI_PMON_CTR0_ADDR = 0xA00;
constexpr auto SERVER_HBM_CH_PMON_BASE_ADDR = 0x141c00;
constexpr auto SERVER_HBM_CH_PMON_STEP = 0x4000;
constexpr auto SERVER_HBM_CH_PMON_SIZE = 0x1000;
constexpr auto SERVER_HBM_BOX_PMON_STEP = 0x9000;
constexpr auto SERVER_MC_CH_PMON_BASE_ADDR = 0x22800;
constexpr auto SERVER_MC_CH_PMON_STEP = 0x4000;
constexpr auto SERVER_MC_CH_PMON_SIZE = 0x1000;
constexpr auto SERVER_MC_CH_PMON_BOX_CTL_OFFSET = 0x00;
constexpr auto SERVER_MC_CH_PMON_CTL0_OFFSET = 0x40;
constexpr auto SERVER_MC_CH_PMON_CTL1_OFFSET = SERVER_MC_CH_PMON_CTL0_OFFSET + 4*1;
constexpr auto SERVER_MC_CH_PMON_CTL2_OFFSET = SERVER_MC_CH_PMON_CTL0_OFFSET + 4*2;
constexpr auto SERVER_MC_CH_PMON_CTL3_OFFSET = SERVER_MC_CH_PMON_CTL0_OFFSET + 4*3;
constexpr auto SERVER_MC_CH_PMON_CTR0_OFFSET = 0x08;
constexpr auto SERVER_MC_CH_PMON_CTR1_OFFSET = SERVER_MC_CH_PMON_CTR0_OFFSET + 8*1;
constexpr auto SERVER_MC_CH_PMON_CTR2_OFFSET = SERVER_MC_CH_PMON_CTR0_OFFSET + 8*2;
constexpr auto SERVER_MC_CH_PMON_CTR3_OFFSET = SERVER_MC_CH_PMON_CTR0_OFFSET + 8*3;
constexpr auto SERVER_MC_CH_PMON_FIXED_CTL_OFFSET = 0x54;
constexpr auto SERVER_MC_CH_PMON_FIXED_CTR_OFFSET = 0x38;
constexpr auto BHS_MC_CH_PMON_BASE_ADDR = 0x024e800;
constexpr auto GNR_D_A_MC_CH_PMON_BASE_ADDR = 0x0104800;
constexpr auto GNR_D_B_MC_CH_PMON_BASE_ADDR = 0x0208800;
constexpr auto JKTIVT_QPI_PORT0_REGISTER_DEV_ADDR = 8;
constexpr auto JKTIVT_QPI_PORT0_REGISTER_FUNC_ADDR = 2;
constexpr auto JKTIVT_QPI_PORT1_REGISTER_DEV_ADDR = 9;
constexpr auto JKTIVT_QPI_PORT1_REGISTER_FUNC_ADDR = 2;
constexpr auto JKTIVT_QPI_PORT2_REGISTER_DEV_ADDR = 24;
constexpr auto JKTIVT_QPI_PORT2_REGISTER_FUNC_ADDR = 2;
constexpr auto HSX_QPI_PORT0_REGISTER_DEV_ADDR = 8;
constexpr auto HSX_QPI_PORT0_REGISTER_FUNC_ADDR = 2;
constexpr auto HSX_QPI_PORT1_REGISTER_DEV_ADDR = 9;
constexpr auto HSX_QPI_PORT1_REGISTER_FUNC_ADDR = 2;
constexpr auto HSX_QPI_PORT2_REGISTER_DEV_ADDR = 10;
constexpr auto HSX_QPI_PORT2_REGISTER_FUNC_ADDR = 2;
constexpr auto SKX_QPI_PORT0_REGISTER_DEV_ADDR = 14;
constexpr auto SKX_QPI_PORT0_REGISTER_FUNC_ADDR = 0;
constexpr auto SKX_QPI_PORT1_REGISTER_DEV_ADDR = 15;
constexpr auto SKX_QPI_PORT1_REGISTER_FUNC_ADDR = 0;
constexpr auto SKX_QPI_PORT2_REGISTER_DEV_ADDR = 16;
constexpr auto SKX_QPI_PORT2_REGISTER_FUNC_ADDR = 0;
constexpr auto CPX_QPI_PORT3_REGISTER_DEV_ADDR = 14;
constexpr auto CPX_QPI_PORT3_REGISTER_FUNC_ADDR = 4;
constexpr auto CPX_QPI_PORT4_REGISTER_DEV_ADDR = 15;
constexpr auto CPX_QPI_PORT4_REGISTER_FUNC_ADDR = 4;
constexpr auto CPX_QPI_PORT5_REGISTER_DEV_ADDR = 16;
constexpr auto CPX_QPI_PORT5_REGISTER_FUNC_ADDR = 4;
constexpr auto ICX_QPI_PORT0_REGISTER_DEV_ADDR = 2;
constexpr auto ICX_QPI_PORT0_REGISTER_FUNC_ADDR = 1;
constexpr auto ICX_QPI_PORT1_REGISTER_DEV_ADDR = 3;
constexpr auto ICX_QPI_PORT1_REGISTER_FUNC_ADDR = 1;
constexpr auto ICX_QPI_PORT2_REGISTER_DEV_ADDR = 4;
constexpr auto ICX_QPI_PORT2_REGISTER_FUNC_ADDR = 1;
constexpr auto SPR_QPI_PORT0_REGISTER_DEV_ADDR = 1;
constexpr auto SPR_QPI_PORT0_REGISTER_FUNC_ADDR = 1;
constexpr auto SPR_QPI_PORT1_REGISTER_DEV_ADDR = 2;
constexpr auto SPR_QPI_PORT1_REGISTER_FUNC_ADDR = 1;
constexpr auto SPR_QPI_PORT2_REGISTER_DEV_ADDR = 3;
constexpr auto SPR_QPI_PORT2_REGISTER_FUNC_ADDR = 1;
constexpr auto SPR_QPI_PORT3_REGISTER_DEV_ADDR = 4;
constexpr auto SPR_QPI_PORT3_REGISTER_FUNC_ADDR = 1;
constexpr auto BHS_QPI_PORT0_REGISTER_DEV_ADDR = 16;
constexpr auto BHS_QPI_PORT0_REGISTER_FUNC_ADDR = 1;
constexpr auto BHS_QPI_PORT1_REGISTER_DEV_ADDR = 17;
constexpr auto BHS_QPI_PORT1_REGISTER_FUNC_ADDR = 1;
constexpr auto BHS_QPI_PORT2_REGISTER_DEV_ADDR = 18;
constexpr auto BHS_QPI_PORT2_REGISTER_FUNC_ADDR = 1;
constexpr auto BHS_QPI_PORT3_REGISTER_DEV_ADDR = 19;
constexpr auto BHS_QPI_PORT3_REGISTER_FUNC_ADDR = 1;
constexpr auto BHS_QPI_PORT4_REGISTER_DEV_ADDR = 20;
constexpr auto BHS_QPI_PORT4_REGISTER_FUNC_ADDR = 1;
constexpr auto BHS_QPI_PORT5_REGISTER_DEV_ADDR = 21;
constexpr auto BHS_QPI_PORT5_REGISTER_FUNC_ADDR = 1;
constexpr auto QPI_PORT0_MISC_REGISTER_FUNC_ADDR = 0;
constexpr auto QPI_PORT1_MISC_REGISTER_FUNC_ADDR = 0;
constexpr auto QPI_PORT2_MISC_REGISTER_FUNC_ADDR = 0;
constexpr auto SKX_M3UPI_PORT0_REGISTER_DEV_ADDR = (0x12);
constexpr auto SKX_M3UPI_PORT0_REGISTER_FUNC_ADDR = (1);
constexpr auto SKX_M3UPI_PORT1_REGISTER_DEV_ADDR = (0x12);
constexpr auto SKX_M3UPI_PORT1_REGISTER_FUNC_ADDR = (2);
constexpr auto SKX_M3UPI_PORT2_REGISTER_DEV_ADDR = (0x12);
constexpr auto SKX_M3UPI_PORT2_REGISTER_FUNC_ADDR = (5);
constexpr auto CPX_M3UPI_PORT0_REGISTER_DEV_ADDR = (0x12);
constexpr auto CPX_M3UPI_PORT0_REGISTER_FUNC_ADDR = (1);
constexpr auto CPX_M3UPI_PORT1_REGISTER_DEV_ADDR = (0x12);
constexpr auto CPX_M3UPI_PORT1_REGISTER_FUNC_ADDR = (2);
constexpr auto CPX_M3UPI_PORT2_REGISTER_DEV_ADDR = (0x13);
constexpr auto CPX_M3UPI_PORT2_REGISTER_FUNC_ADDR = (1);
constexpr auto CPX_M3UPI_PORT3_REGISTER_DEV_ADDR = (0x13);
constexpr auto CPX_M3UPI_PORT3_REGISTER_FUNC_ADDR = (2);
constexpr auto CPX_M3UPI_PORT4_REGISTER_DEV_ADDR = (0x14);
constexpr auto CPX_M3UPI_PORT4_REGISTER_FUNC_ADDR = (1);
constexpr auto CPX_M3UPI_PORT5_REGISTER_DEV_ADDR = (0x14);
constexpr auto CPX_M3UPI_PORT5_REGISTER_FUNC_ADDR = (2);
constexpr auto ICX_M3UPI_PORT0_REGISTER_DEV_ADDR = (5);
constexpr auto ICX_M3UPI_PORT1_REGISTER_DEV_ADDR = (6);
constexpr auto ICX_M3UPI_PORT2_REGISTER_DEV_ADDR = (7);
constexpr auto ICX_M3UPI_PORT0_REGISTER_FUNC_ADDR = (1);
constexpr auto ICX_M3UPI_PORT1_REGISTER_FUNC_ADDR = (1);
constexpr auto ICX_M3UPI_PORT2_REGISTER_FUNC_ADDR = (1);
constexpr auto SPR_M3UPI_PORT0_REGISTER_DEV_ADDR = 5;
constexpr auto SPR_M3UPI_PORT1_REGISTER_DEV_ADDR = 6;
constexpr auto SPR_M3UPI_PORT2_REGISTER_DEV_ADDR = 7;
constexpr auto SPR_M3UPI_PORT3_REGISTER_DEV_ADDR = 8;
constexpr auto SPR_M3UPI_PORT0_REGISTER_FUNC_ADDR = 1;
constexpr auto SPR_M3UPI_PORT1_REGISTER_FUNC_ADDR = 1;
constexpr auto SPR_M3UPI_PORT2_REGISTER_FUNC_ADDR = 1;
constexpr auto SPR_M3UPI_PORT3_REGISTER_FUNC_ADDR = 1;
constexpr auto SKX_M2M_0_REGISTER_DEV_ADDR = 8;
constexpr auto SKX_M2M_0_REGISTER_FUNC_ADDR = 0;
constexpr auto SKX_M2M_1_REGISTER_DEV_ADDR = 9;
constexpr auto SKX_M2M_1_REGISTER_FUNC_ADDR = 0;
constexpr auto SERVER_M2M_0_REGISTER_DEV_ADDR = 12;
constexpr auto SERVER_M2M_0_REGISTER_FUNC_ADDR = 0;
constexpr auto SERVER_M2M_1_REGISTER_DEV_ADDR = 13;
constexpr auto SERVER_M2M_1_REGISTER_FUNC_ADDR = 0;
constexpr auto SERVER_M2M_2_REGISTER_DEV_ADDR = 14;
constexpr auto SERVER_M2M_2_REGISTER_FUNC_ADDR = 0;
constexpr auto SERVER_M2M_3_REGISTER_DEV_ADDR = 15;
constexpr auto SERVER_M2M_3_REGISTER_FUNC_ADDR = 0;
constexpr auto SERVER_HBM_M2M_0_REGISTER_DEV_ADDR = 12;
constexpr auto SERVER_HBM_M2M_0_REGISTER_FUNC_ADDR = 1;
constexpr auto SERVER_HBM_M2M_1_REGISTER_DEV_ADDR = 13;
constexpr auto SERVER_HBM_M2M_1_REGISTER_FUNC_ADDR = 1;
constexpr auto SERVER_HBM_M2M_2_REGISTER_DEV_ADDR = 14;
constexpr auto SERVER_HBM_M2M_2_REGISTER_FUNC_ADDR = 1;
constexpr auto SERVER_HBM_M2M_3_REGISTER_DEV_ADDR = 15;
constexpr auto SERVER_HBM_M2M_3_REGISTER_FUNC_ADDR = 1;
constexpr auto SERVER_HBM_M2M_4_REGISTER_DEV_ADDR = 12;
constexpr auto SERVER_HBM_M2M_4_REGISTER_FUNC_ADDR = 2;
constexpr auto SERVER_HBM_M2M_5_REGISTER_DEV_ADDR = 13;
constexpr auto SERVER_HBM_M2M_5_REGISTER_FUNC_ADDR = 2;
constexpr auto SERVER_HBM_M2M_6_REGISTER_DEV_ADDR = 14;
constexpr auto SERVER_HBM_M2M_6_REGISTER_FUNC_ADDR = 2;
constexpr auto SERVER_HBM_M2M_7_REGISTER_DEV_ADDR = 15;
constexpr auto SERVER_HBM_M2M_7_REGISTER_FUNC_ADDR = 2;
constexpr auto SERVER_HBM_M2M_8_REGISTER_DEV_ADDR = 12;
constexpr auto SERVER_HBM_M2M_8_REGISTER_FUNC_ADDR = 3;
constexpr auto SERVER_HBM_M2M_9_REGISTER_DEV_ADDR = 13;
constexpr auto SERVER_HBM_M2M_9_REGISTER_FUNC_ADDR = 3;
constexpr auto SERVER_HBM_M2M_10_REGISTER_DEV_ADDR = 14;
constexpr auto SERVER_HBM_M2M_10_REGISTER_FUNC_ADDR = 3;
constexpr auto SERVER_HBM_M2M_11_REGISTER_DEV_ADDR = 15;
constexpr auto SERVER_HBM_M2M_11_REGISTER_FUNC_ADDR = 3;
constexpr auto SERVER_HBM_M2M_12_REGISTER_DEV_ADDR = 12;
constexpr auto SERVER_HBM_M2M_12_REGISTER_FUNC_ADDR = 4;
constexpr auto SERVER_HBM_M2M_13_REGISTER_DEV_ADDR = 13;
constexpr auto SERVER_HBM_M2M_13_REGISTER_FUNC_ADDR = 4;
constexpr auto SERVER_HBM_M2M_14_REGISTER_DEV_ADDR = 14;
constexpr auto SERVER_HBM_M2M_14_REGISTER_FUNC_ADDR = 4;
constexpr auto SERVER_HBM_M2M_15_REGISTER_DEV_ADDR = 15;
constexpr auto SERVER_HBM_M2M_15_REGISTER_FUNC_ADDR = 4;
// BHS B2CMI (M2M)
constexpr auto BHS_M2M_0_REGISTER_DEV_ADDR = 5;
constexpr auto BHS_M2M_0_REGISTER_FUNC_ADDR = 1;
constexpr auto BHS_M2M_1_REGISTER_DEV_ADDR = 5;
constexpr auto BHS_M2M_1_REGISTER_FUNC_ADDR = 2;
constexpr auto BHS_M2M_2_REGISTER_DEV_ADDR = 5;
constexpr auto BHS_M2M_2_REGISTER_FUNC_ADDR = 3;
constexpr auto BHS_M2M_3_REGISTER_DEV_ADDR = 5;
constexpr auto BHS_M2M_3_REGISTER_FUNC_ADDR = 4;
constexpr auto BHS_M2M_4_REGISTER_DEV_ADDR = 5;
constexpr auto BHS_M2M_4_REGISTER_FUNC_ADDR = 5;
constexpr auto BHS_M2M_5_REGISTER_DEV_ADDR = 5;
constexpr auto BHS_M2M_5_REGISTER_FUNC_ADDR = 6;
constexpr auto BHS_M2M_6_REGISTER_DEV_ADDR = 5;
constexpr auto BHS_M2M_6_REGISTER_FUNC_ADDR = 7;
constexpr auto BHS_M2M_7_REGISTER_DEV_ADDR = 6;
constexpr auto BHS_M2M_7_REGISTER_FUNC_ADDR = 1;
constexpr auto BHS_M2M_8_REGISTER_DEV_ADDR = 6;
constexpr auto BHS_M2M_8_REGISTER_FUNC_ADDR = 2;
constexpr auto BHS_M2M_9_REGISTER_DEV_ADDR = 6;
constexpr auto BHS_M2M_9_REGISTER_FUNC_ADDR = 3;
constexpr auto BHS_M2M_10_REGISTER_DEV_ADDR = 6;
constexpr auto BHS_M2M_10_REGISTER_FUNC_ADDR = 4;
constexpr auto BHS_M2M_11_REGISTER_DEV_ADDR = 6;
constexpr auto BHS_M2M_11_REGISTER_FUNC_ADDR = 5;
// BHS B2UPI (M3UPI)
constexpr auto BHS_M3UPI_PORT0_REGISTER_DEV_ADDR = 24;
constexpr auto BHS_M3UPI_PORT1_REGISTER_DEV_ADDR = 25;
constexpr auto BHS_M3UPI_PORT2_REGISTER_DEV_ADDR = 26;
constexpr auto BHS_M3UPI_PORT3_REGISTER_DEV_ADDR = 27;
constexpr auto BHS_M3UPI_PORT4_REGISTER_DEV_ADDR = 28;
constexpr auto BHS_M3UPI_PORT5_REGISTER_DEV_ADDR = 29;
constexpr auto BHS_M3UPI_PORT0_REGISTER_FUNC_ADDR = 0;
constexpr auto BHS_M3UPI_PORT1_REGISTER_FUNC_ADDR = 0;
constexpr auto BHS_M3UPI_PORT2_REGISTER_FUNC_ADDR = 0;
constexpr auto BHS_M3UPI_PORT3_REGISTER_FUNC_ADDR = 0;
constexpr auto BHS_M3UPI_PORT4_REGISTER_FUNC_ADDR = 0;
constexpr auto BHS_M3UPI_PORT5_REGISTER_FUNC_ADDR = 0;
constexpr auto SKX_M2M_PCI_PMON_BOX_CTL_ADDR = 0x258;
constexpr auto SKX_M2M_PCI_PMON_CTL0_ADDR = 0x228;
constexpr auto SKX_M2M_PCI_PMON_CTL1_ADDR = 0x230;
constexpr auto SKX_M2M_PCI_PMON_CTL2_ADDR = 0x238;
constexpr auto SKX_M2M_PCI_PMON_CTL3_ADDR = 0x240;
constexpr auto SKX_M2M_PCI_PMON_CTR0_ADDR = 0x200;
constexpr auto SKX_M2M_PCI_PMON_CTR1_ADDR = 0x208;
constexpr auto SKX_M2M_PCI_PMON_CTR2_ADDR = 0x210;
constexpr auto SKX_M2M_PCI_PMON_CTR3_ADDR = 0x218;
constexpr auto SERVER_M2M_PCI_PMON_BOX_CTL_ADDR = 0x438;
constexpr auto SERVER_M2M_PCI_PMON_CTL0_ADDR = 0x468;
constexpr auto SERVER_M2M_PCI_PMON_CTL1_ADDR = SERVER_M2M_PCI_PMON_CTL0_ADDR + 1*8;
constexpr auto SERVER_M2M_PCI_PMON_CTL2_ADDR = SERVER_M2M_PCI_PMON_CTL0_ADDR + 2*8;
constexpr auto SERVER_M2M_PCI_PMON_CTL3_ADDR = SERVER_M2M_PCI_PMON_CTL0_ADDR + 3*8;
constexpr auto SERVER_M2M_PCI_PMON_CTR0_ADDR = 0x440;
constexpr auto SERVER_M2M_PCI_PMON_CTR1_ADDR = SERVER_M2M_PCI_PMON_CTR0_ADDR + 1*8;
constexpr auto SERVER_M2M_PCI_PMON_CTR2_ADDR = SERVER_M2M_PCI_PMON_CTR0_ADDR + 2*8;
constexpr auto SERVER_M2M_PCI_PMON_CTR3_ADDR = SERVER_M2M_PCI_PMON_CTR0_ADDR + 3*8;
constexpr auto M3UPI_PCI_PMON_BOX_CTL_ADDR = (0xF4);
constexpr auto M3UPI_PCI_PMON_CTL0_ADDR = (0xD8);
constexpr auto M3UPI_PCI_PMON_CTL1_ADDR = (0xDC);
constexpr auto M3UPI_PCI_PMON_CTL2_ADDR = (0xE0);
constexpr auto M3UPI_PCI_PMON_CTR0_ADDR = (0xA0);
constexpr auto M3UPI_PCI_PMON_CTR1_ADDR = (0xA8);
constexpr auto M3UPI_PCI_PMON_CTR2_ADDR = (0xB0);
constexpr auto ICX_M3UPI_PCI_PMON_BOX_CTL_ADDR = (0xA0);
constexpr auto ICX_M3UPI_PCI_PMON_CTL0_ADDR = (0xD8);
constexpr auto ICX_M3UPI_PCI_PMON_CTL1_ADDR = (0xDC);
constexpr auto ICX_M3UPI_PCI_PMON_CTL2_ADDR = (0xE0);
constexpr auto ICX_M3UPI_PCI_PMON_CTL3_ADDR = (0xE4);
constexpr auto ICX_M3UPI_PCI_PMON_CTR0_ADDR = (0xA8);
constexpr auto ICX_M3UPI_PCI_PMON_CTR1_ADDR = (0xB0);
constexpr auto ICX_M3UPI_PCI_PMON_CTR2_ADDR = (0xB8);
constexpr auto ICX_M3UPI_PCI_PMON_CTR3_ADDR = (0xC0);
constexpr auto BHS_M3UPI_PCI_PMON_BOX_CTL_ADDR = (0x408);
constexpr auto BHS_M3UPI_PCI_PMON_CTL0_ADDR = (0x430);
constexpr auto BHS_M3UPI_PCI_PMON_CTL1_ADDR = (0x438);
constexpr auto BHS_M3UPI_PCI_PMON_CTL2_ADDR = (0x440);
constexpr auto BHS_M3UPI_PCI_PMON_CTL3_ADDR = (0x448);
constexpr auto BHS_M3UPI_PCI_PMON_CTR0_ADDR = (0x410);
constexpr auto BHS_M3UPI_PCI_PMON_CTR1_ADDR = (0x418);
constexpr auto BHS_M3UPI_PCI_PMON_CTR2_ADDR = (0x420);
constexpr auto BHS_M3UPI_PCI_PMON_CTR3_ADDR = (0x428);
constexpr auto MSR_UNCORE_PMON_GLOBAL_CTL = 0x700;
constexpr auto IVT_MSR_UNCORE_PMON_GLOBAL_CTL = 0x0C00;
constexpr auto SPR_MSR_UNCORE_PMON_GLOBAL_CTL = 0x2FF0;
constexpr auto PCM_INVALID_DEV_ADDR = ~(uint32)0UL;
constexpr auto PCM_INVALID_FUNC_ADDR = ~(uint32)0UL;
constexpr auto Q_P_PCI_PMON_BOX_CTL_ADDR = 0x0F4;
constexpr auto Q_P_PCI_PMON_CTL3_ADDR = 0x0E4;
constexpr auto Q_P_PCI_PMON_CTL2_ADDR = 0x0E0;
constexpr auto Q_P_PCI_PMON_CTL1_ADDR = 0x0DC;
constexpr auto Q_P_PCI_PMON_CTL0_ADDR = 0x0D8;
constexpr auto Q_P_PCI_PMON_CTR3_ADDR = 0x0B8;
constexpr auto Q_P_PCI_PMON_CTR2_ADDR = 0x0B0;
constexpr auto Q_P_PCI_PMON_CTR1_ADDR = 0x0A8;
constexpr auto Q_P_PCI_PMON_CTR0_ADDR = 0x0A0;
constexpr auto QPI_RATE_STATUS_ADDR = 0x0D4;
constexpr auto U_L_PCI_PMON_BOX_CTL_ADDR = 0x378;
constexpr auto U_L_PCI_PMON_CTL3_ADDR = 0x368;
constexpr auto U_L_PCI_PMON_CTL2_ADDR = 0x360;
constexpr auto U_L_PCI_PMON_CTL1_ADDR = 0x358;
constexpr auto U_L_PCI_PMON_CTL0_ADDR = 0x350;
constexpr auto U_L_PCI_PMON_CTR3_ADDR = 0x330;
constexpr auto U_L_PCI_PMON_CTR2_ADDR = 0x328;
constexpr auto U_L_PCI_PMON_CTR1_ADDR = 0x320;
constexpr auto U_L_PCI_PMON_CTR0_ADDR = 0x318;
constexpr auto ICX_UPI_PCI_PMON_BOX_CTL_ADDR = 0x318;
constexpr auto ICX_UPI_PCI_PMON_CTL3_ADDR = 0x368;
constexpr auto ICX_UPI_PCI_PMON_CTL2_ADDR = 0x360;
constexpr auto ICX_UPI_PCI_PMON_CTL1_ADDR = 0x358;
constexpr auto ICX_UPI_PCI_PMON_CTL0_ADDR = 0x350;
constexpr auto ICX_UPI_PCI_PMON_CTR3_ADDR = 0x338;
constexpr auto ICX_UPI_PCI_PMON_CTR2_ADDR = 0x330;
constexpr auto ICX_UPI_PCI_PMON_CTR1_ADDR = 0x328;
constexpr auto ICX_UPI_PCI_PMON_CTR0_ADDR = 0x320;
constexpr auto SPR_UPI_PCI_PMON_BOX_CTL_ADDR = 0x318;
constexpr auto SPR_UPI_PCI_PMON_CTL0_ADDR = 0x350;
constexpr auto SPR_UPI_PCI_PMON_CTR0_ADDR = 0x320;
constexpr auto UCLK_FIXED_CTR_ADDR = 0x704;