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ready for first release

mnemocronpushed 1 commit to main • c643f77…dc58d8d • 
on Apr 20, 2024

updated images for blogpost

mnemocronpushed 1 commit to main • 2a8b46d…c643f77 • 
on Apr 17, 2024

fix bugs in compiler, add another slice -> working :D

mnemocronpushed 1 commit to main • bd99ead…2a8b46d • 
on Apr 14, 2024

working compiler :)

mnemocronpushed 1 commit to main • 2afae8b…bd99ead • 
on Apr 14, 2024

bitstream compiler WIP

mnemocronpushed 1 commit to main • 06ac86b…2afae8b • 
on Apr 14, 2024

built a working "compiler" in C for Arduino

mnemocronpushed 1 commit to main • 924edd9…06ac86b • 
on Apr 13, 2024

unfinished test: 4-bit counter

mnemocronpushed 1 commit to main • e90dfe8…924edd9 • 
on Mar 17, 2024

cleanup repository

mnemocronpushed 1 commit to main • 6e0655a…e90dfe8 • 
on Mar 17, 2024

cleanup architecture

mnemocronpushed 1 commit to main • f00666f…6e0655a • 
on Mar 16, 2024

remove final occurrences of the word "prio"

mnemocronpushed 1 commit to main • 2a27b1c…f00666f • 
on Mar 14, 2024

refactor VHDL to remove "prio" bus and merge into regular bus(5 downt…

mnemocronpushed 1 commit to main • 08c1d3f…2a27b1c • 
on Mar 14, 2024

delete latex doc

mnemocronpushed 1 commit to main • 609369c…08c1d3f • 
on Mar 8, 2024

update README before pulishing

mnemocronpushed 1 commit to main • e33731c…609369c • 
on Mar 8, 2024

fixed CE throughout simulation

mnemocronpushed 1 commit to main • 4131375…e33731c • 
on Mar 8, 2024

include CE in CLB

mnemocronpushed 3 commits to main • 879aab8…4131375 • 
on Mar 4, 2024

fix wrong bitstream order

mnemocronpushed 1 commit to main • 1ac72e0…879aab8 • 
on Feb 25, 2024

first working tests on a full hardware slice

mnemocronpushed 1 commit to main • b74c649…1ac72e0 • 
on Feb 21, 2024

rm files

mnemocronpushed 2 commits to main • cde035d…b74c649 • 
on Feb 20, 2024

PCB renders

mnemocronpushed 2 commits to main • 03ad331…cde035d • 
on Feb 13, 2024

start new feature CE

mnemocronpushed 1 commit to main • 00e6bd8…03ad331 • 
on Jan 18, 2024

CLB slice rev. 2.0

mnemocronpushed 1 commit to main • fcab69e…00e6bd8 • 
on Jan 17, 2024

CLB requires rev.2

mnemocronpushed 1 commit to main • 0531415…fcab69e • 
on Jan 15, 2024

more kicad layouts 2.

mnemocronpushed 1 commit to main • f0c4402…0531415 • 
on Jan 10, 2024

more kicad layouts

mnemocronpushed 2 commits to main • 9875f46…f0c4402 • 
on Jan 8, 2024

sw box layout almost complete

mnemocronpushed 1 commit to main • eb878d7…9875f46 • 
on Jan 6, 2024

verified matching bitstream between PCB and VHDL

mnemocronpushed 1 commit to main • e918ef0…eb878d7 • 
on Jan 4, 2024

SWbox layout nearly complete

mnemocronpushed 1 commit to main • 247fdc0…e918ef0 • 
on Jan 3, 2024

start layout of SW box

mnemocronpushed 1 commit to main • b4a6212…247fdc0 • 
on Jan 2, 2024

Merge branch 'main' of github.com:mnemocron/my-discrete-fpga into main

mnemocronpushed 3 commits to main • 706a892…b4a6212 • 
on Jan 2, 2024

Update fpga-bitstream-test.ino

mnemocronpushed 1 commit to main • c80c7b9…706a892 • 
on Dec 30, 2023