ready for first release

- fixed Arduino compiler
- more documentation
- tested SUM mode on 3 Tiles (physical PCB)

Author: mnemocron

README.md

@@ -1,11 +1,12 @@
 # Discrete 7400 logic based FPGA
-A custom, modular FPGA architecture simulated in VHDL (GHDL), realized with discrete 7400-logic ICs and layouted on PCB with KiCAD.
+A custom, modular FPGA architecture simulated in VHDL (GHDL), realized with discrete 7400-logic ICs, layouted on PCB with KiCAD and programmed through an abstraction layer via Arduino.
 
 ---
 
-![doc/img/architecture-tile.png](doc/img/architecture-tile.png)
+![doc/img/fpga-arduino-1.jpg](doc/img/fpga-arduino-1.jpg)
 
-Read more on my blog: [mnemocron.github.io](https://mnemocron.github.io/2023-12-08-DIY-FPGA-diary-1/)
+Read the full thorugh process and many explanations on my blog: 
+[mnemocron.github.io](https://mnemocron.github.io/2023-12-08-DIY-FPGA-diary-0/)
 
 ## Motivation
 
@@ -15,8 +16,12 @@ Ever since building Ben Eaters [8 bit CPU](https://eater.net/8bit) myself, I wan
 The 8 bit CPU is arguably the worst CPU ever built - but it is a fantastic educational example.
 And that is the case for the **4 bit FPGA**. It is a purely educational side project that boosted my knowledge about FPGA architecture, VHDL design and verification. Without further ado, here it is.
 
+![doc/img/architecture-tile.png](doc/img/architecture-tile.png)
+
 ## Build Process
 
+The actual part list is WIP. Expected material cost are approximately 50 USD per assembled tile (4:4 bit LUT with interconnect).
+
 ![doc/img/concept-to-pcb.png](doc/img/concept-to-pcb.png)
 
 ---
@@ -32,9 +37,15 @@ Head straight to the `./vhdl/test` directory to see examples with the full FPGA
 - `./architecture` contains conceptual draw.io block diagrams
 - `./doc` contains images, notes and tools that may be helpful
 - `./ihdl` (WIP) contains ideas and concepts for a "compiler"
-- `./kicad` contains schematics and PCB files for KiCAD 7.0
-- `./sketch` contains Arduino code for testing of assembled PCB hardware
-- `./vhdl` contains models for 74xx ICs and the full FPGA architecture
+- `./kicad` contains **schematics and PCB files** for KiCAD 7.0
+- `./sketch` contains Arduino code for testing of assembled PCB hardware and **abstraction layer in C**
+- `./vhdl` contains models for 74xx ICs and the **full FPGA architecture for simulation**
+
+---
+
+## "Assemble" code to map onto the FPGA in Arduino
+
+![doc/img/compiler-design.png](doc/img/compiler-design.png)
 
 ---
 

doc/img/compiler-design.png

@@ -22,7 +22,7 @@
 #define CLOCK_PIN 8
 #define RST_PIN 9
 
-#define CLOCK_HALF_PERIOD 250
+#define CLOCK_HALF_PERIOD 50
 
 FILE f_out;
 int sput(char c, __attribute__((unused)) FILE* f) {return !Serial.write(c);}

doc/img/fpga-arduino-1.jpg

@@ -143,6 +143,7 @@ int create_bitstream(fpga_t* fpga){
       // CLB
       clb_t* clb = &slc->clb;
       SET_CLB_LUT_BITSTREAM(slc);
+      SET_CLB_INMUX_BITSTREAM(slc);
       for(int i=0; i<4; i++){
         if(clb->reg[i])
           SET_BIT_IN_BITSTREAM(slc, 15-i);

doc/lut_truth_table.xlsx

@@ -48,7 +48,8 @@ void diyfpga_setup(){
   myfpga.slice[0][0].cbh.sel[1] = BUS_2;
   myfpga.slice[0][0].cbh.sel[2] = BUS_1;
   myfpga.slice[0][0].cbh.sel[3] = BUS_0;
-  
+
+  /*
   myfpga.slice[0][1].sw.north[0] = true;
   myfpga.slice[0][1].sw.north[1] = true;
   myfpga.slice[0][1].sw.north[2] = true;
@@ -77,6 +78,70 @@ void diyfpga_setup(){
   myfpga.slice[0][1].sw.north[5] = true;
   myfpga.slice[0][1].sw.south[4] = true;
   myfpga.slice[0][1].sw.south[5] = true;
+  */
+
+  myfpga.slice[0][1].sw.north[0] = true;
+  myfpga.slice[0][1].sw.north[1] = true;
+  myfpga.slice[0][1].sw.north[2] = true;
+  myfpga.slice[0][1].sw.north[3] = true;
+  myfpga.slice[0][1].sw.west[0] = true;
+  myfpga.slice[0][1].sw.west[1] = true;
+  myfpga.slice[0][1].sw.west[2] = true;
+  myfpga.slice[0][1].sw.west[3] = true;
+  myfpga.slice[0][1].sw.xp[0] = true;
+  myfpga.slice[0][1].sw.xp[1] = true;
+  myfpga.slice[0][1].sw.xp[2] = true;
+  myfpga.slice[0][1].sw.xp[3] = true;
+  myfpga.slice[0][1].clb.reg[0] = true;
+  myfpga.slice[0][1].clb.reg[1] = true;
+  myfpga.slice[0][1].clb.reg[2] = true;
+  myfpga.slice[0][1].clb.reg[3] = true;
+  myfpga.slice[0][1].clb.sum = true;
+  myfpga.slice[0][0].clb.clk_sel = 0;
+  myfpga.slice[0][0].clb.clk_en = false;
+  myfpga.slice[0][1].clb.in_mux[0] = SUM_INPUT;
+  myfpga.slice[0][1].clb.in_mux[1] = SUM_INPUT;
+  myfpga.slice[0][1].clb.in_mux[2] = SUM_INPUT;
+  myfpga.slice[0][1].clb.in_mux[3] = SUM_INPUT;
+  myfpga.slice[0][1].clb.lut[0] = 0x6;
+  myfpga.slice[0][1].clb.lut[1] = 0x6;
+  myfpga.slice[0][1].clb.lut[2] = 0x6;
+  myfpga.slice[0][1].clb.lut[3] = 0x6;
+  myfpga.slice[0][1].cbv.bus[0] = true;
+  myfpga.slice[0][1].cbv.bus[1] = true;
+  myfpga.slice[0][1].cbv.bus[2] = true;
+  myfpga.slice[0][1].cbv.bus[3] = true;
+
+  myfpga.slice[0][2].clb.reg[0] = true;
+  myfpga.slice[0][2].clb.reg[1] = true;
+  myfpga.slice[0][2].clb.reg[2] = true;
+  myfpga.slice[0][2].clb.reg[3] = true;
+  myfpga.slice[0][2].clb.clk_sel = 0;
+  myfpga.slice[0][2].clb.clk_en = false;
+  myfpga.slice[0][2].clb.sum = false;
+
+  myfpga.slice[0][2].clb.lut[0] = 0x1; // 0x00FF;
+  myfpga.slice[0][2].clb.lut[1] = 0x0; // 0x0FF0; 
+  myfpga.slice[0][2].clb.lut[2] = 0x0; // 0x3CCC; 
+  myfpga.slice[0][2].clb.lut[3] = 0x0; // 0x6AAA; 
+
+  myfpga.slice[0][2].cbv.bus[0] = true;
+  myfpga.slice[0][2].cbv.bus[1] = true;
+  myfpga.slice[0][2].cbv.bus[2] = true;
+  myfpga.slice[0][2].cbv.bus[3] = true;
+
+  myfpga.slice[0][2].sw.xp[0] = true;
+  myfpga.slice[0][2].sw.xp[1] = true;
+  myfpga.slice[0][2].sw.xp[2] = true;
+  myfpga.slice[0][2].sw.xp[3] = true;
+  myfpga.slice[0][2].sw.south[0] = true;
+  myfpga.slice[0][2].sw.south[1] = true;
+  myfpga.slice[0][2].sw.south[2] = true;
+  myfpga.slice[0][2].sw.south[3] = true;
+  myfpga.slice[0][2].sw.west[0] = true;
+  myfpga.slice[0][2].sw.west[1] = true;
+  myfpga.slice[0][2].sw.west[2] = true;
+  myfpga.slice[0][2].sw.west[3] = true;
 
 }
 

sketch/diyfpga-compile/diyfpga-compile.ino

@@ -12,7 +12,7 @@
 
 // How many slices does the FPGA have? (2D matrix)
 #define N_SLICE_X (1)
-#define N_SLICE_Y (2)
+#define N_SLICE_Y (3)
 
 #define ENABLE_PRINT_MESSAGES false