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decode.c
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/*
* rv32emu is freely redistributable under the MIT License. See the file
* "LICENSE" for information on usage and redistribution of this file.
*/
#include <assert.h>
#include <stdlib.h>
#include "decode.h"
#include "riscv_private.h"
/* decode rd field
* rd = insn[11:7]
*/
static inline uint32_t decode_rd(const uint32_t insn)
{
return (insn & FR_RD) >> 7;
}
/* decode rs1 field.
* rs1 = insn[19:15]
*/
static inline uint32_t decode_rs1(const uint32_t insn)
{
return (insn & FR_RS1) >> 15;
}
/* decode rs2 field.
* rs2 = insn[24:20]
*/
static inline uint32_t decode_rs2(const uint32_t insn)
{
return (insn & FR_RS2) >> 20;
}
/* decoded funct3 field.
* funct3 = insn[14:12]
*/
static inline uint32_t decode_funct3(const uint32_t insn)
{
return (insn & FR_FUNCT3) >> 12;
}
/* decode funct7 field.
* funct7 = insn[31:25]
*/
static inline uint32_t decode_funct7(const uint32_t insn)
{
return (insn & FR_FUNCT7) >> 25;
}
/* decode U-type instruction immediate.
* imm[31:12] = insn[31:12]
*/
static inline uint32_t decode_utype_imm(const uint32_t insn)
{
return insn & FU_IMM_31_12;
}
/* decode J-type instruction immediate.
* imm[20|10:1|11|19:12] = insn[31|30:21|20|19:12]
*/
static inline int32_t decode_jtype_imm(const uint32_t insn)
{
uint32_t dst = 0;
dst |= (insn & FJ_IMM_20);
dst |= (insn & FJ_IMM_19_12) << 11;
dst |= (insn & FJ_IMM_11) << 2;
dst |= (insn & FJ_IMM_10_1) >> 9;
/* NOTE: shifted to 2nd least significant bit */
return ((int32_t) dst) >> 11;
}
/* decode I-type instruction immediate.
* imm[11:0] = insn[31:20]
*/
static inline int32_t decode_itype_imm(const uint32_t insn)
{
return ((int32_t) (insn & FI_IMM_11_0)) >> 20;
}
/* decode B-type instruction immediate.
* imm[12] = insn[31]
* imm[11] = insn[7]
* imm[10:5] = insn[30:25]
* imm[4:1] = insn[11:8]
*/
static inline int32_t decode_btype_imm(const uint32_t insn)
{
uint32_t dst = 0;
dst |= (insn & FB_IMM_12);
dst |= (insn & FB_IMM_11) << 23;
dst |= (insn & FB_IMM_10_5) >> 1;
dst |= (insn & FB_IMM_4_1) << 12;
/* NOTE: shifted to 2nd least significant bit */
return ((int32_t) dst) >> 19;
}
/* decode S-type instruction immediate.
* imm[11:5] = insn[31:25]
* imm[4:0] = insn[11:7]
*/
static inline int32_t decode_stype_imm(const uint32_t insn)
{
uint32_t dst = 0;
dst |= (insn & FS_IMM_11_5);
dst |= (insn & FS_IMM_4_0) << 13;
return ((int32_t) dst) >> 20;
}
#if RV32_HAS(EXT_F)
/* decode R4-type rs3 field
* rs3 = inst[31:27]
*/
static inline uint32_t decode_r4type_rs3(const uint32_t insn)
{
return (insn & FR4_RS3) >> 27;
}
#endif
#if RV32_HAS(EXT_C)
enum {
/* clang-format off */
/* ....xxxx....xxxx */
CJ_IMM_11 = 0b0001000000000000,
CJ_IMM_4 = 0b0000100000000000,
CJ_IMM_9_8 = 0b0000011000000000,
CJ_IMM_10 = 0b0000000100000000,
CJ_IMM_6 = 0b0000000010000000,
CJ_IMM_7 = 0b0000000001000000,
CJ_IMM_3_1 = 0b0000000000111000,
CJ_IMM_5 = 0b0000000000000100,
/* ....xxxx....xxxx */
CB_SHAMT_5 = 0b0001000000000000,
CB_SHAMT_4_0 = 0b0000000001111100,
/* clang-format on */
};
/* decode rs1 field
* rs1 = inst[11:7]
*/
static inline uint16_t c_decode_rs1(const uint16_t insn)
{
return (uint16_t) ((insn & FC_RS1) >> 7U);
}
/* decode rs2 field
* rs2 = inst[6:2]
*/
static inline uint16_t c_decode_rs2(const uint16_t insn)
{
return (uint16_t) ((insn & FC_RS2) >> 2U);
}
/* decode rd field
* rd = inst[11:7]
*/
static inline uint16_t c_decode_rd(const uint16_t insn)
{
return (uint16_t) ((insn & FC_RD) >> 7U);
}
/* decode rs1' field
* rs1' = inst[9:7]
*/
static inline uint16_t c_decode_rs1c(const uint16_t insn)
{
return (uint16_t) ((insn & FC_RS1C) >> 7U);
}
/* decode rs2' field
* rs2' = inst[4:2]
*/
static inline uint16_t c_decode_rs2c(const uint16_t insn)
{
return (uint16_t) ((insn & FC_RS2C) >> 2U);
}
/* decode rd' field
* rd' = inst[4:2]
*/
static inline uint16_t c_decode_rdc(const uint16_t insn)
{
return (uint16_t) ((insn & FC_RDC) >> 2U);
}
/* decode C.ADDI4SPN nzuimm field
* nzuimm[5:4|9:6|2|3] = inst[]
*/
static inline uint16_t c_decode_caddi4spn_nzuimm(const uint16_t insn)
{
uint16_t tmp = 0;
tmp |= (insn & 0x1800) >> 7;
tmp |= (insn & 0x780) >> 1;
tmp |= (insn & 0x40) >> 4;
tmp |= (insn & 0x20) >> 2;
return tmp;
}
/* decode C.ADDI16SP nzimm field
* nzimm[9] = inst[12]
* nzimm[4|6|8:7|5] = inst[6:2]
*/
static inline int32_t c_decode_caddi16sp_nzimm(const uint16_t insn)
{
int32_t tmp = (insn & 0x1000) >> 3;
tmp |= (insn & 0x40) >> 2;
tmp |= (insn & 0x20) << 1;
tmp |= (insn & 0x18) << 4;
tmp |= (insn & 0x4) << 3;
return (tmp & 0x200) ? (0xfffffc00 | tmp) : (uint32_t) tmp;
}
/* decode C.LUI nzimm field
* nzimm[17] = inst[12]
* nzimm[16:12] = inst[6:2]
*/
static inline uint32_t c_decode_clui_nzimm(const uint16_t insn)
{
uint32_t tmp = (insn & 0x1000) << 5 | (insn & 0x7c) << 10;
return (tmp & 0x20000) ? (0xfffc0000 | tmp) : tmp;
}
static inline int32_t c_decode_caddi_imm(const uint16_t insn)
{
int32_t tmp = 0;
uint16_t mask = (0x1000 & insn) << 3;
for (int i = 0; i <= 10; ++i)
tmp |= (mask >> i);
tmp |= (insn & 0x007C) >> 2;
return sign_extend_h(tmp);
}
/* decode CI-Format instruction immediate
* imm[5] = inst[12]
* imm[4:0] = inst[6:2]
*/
static inline int32_t c_decode_citype_imm(const uint16_t insn)
{
uint32_t tmp = ((insn & FCI_IMM_12) >> 7) | ((insn & FCI_IMM_6_2) >> 2);
return (tmp & 0x20) ? (int32_t) (0xffffffc0 | tmp) : (int32_t) tmp;
}
/* decode CJ-format instruction immediate
* imm[11] = inst[12]
* imm[10] = inst[8]
* imm[9:8] = inst[10:9]
* imm[7] = inst[6]
* imm[6] = inst[7]
* imm[5] = inst[2]
* imm[4] = inst[11]
* imm[3:1] = inst[5:3]
*/
static inline int32_t c_decode_cjtype_imm(const uint16_t insn)
{
uint16_t tmp = 0;
tmp |= (insn & CJ_IMM_3_1) >> 2;
tmp |= (insn & CJ_IMM_4) >> 7;
tmp |= (insn & CJ_IMM_5) << 3;
tmp |= (insn & CJ_IMM_6) >> 1;
tmp |= (insn & CJ_IMM_7) << 1;
tmp |= (insn & CJ_IMM_9_8) >> 1;
tmp |= (insn & CJ_IMM_10) << 2;
tmp |= (insn & CJ_IMM_11) >> 1;
for (int i = 1; i <= 4; ++i)
tmp |= (0x0800 & tmp) << i;
/* extend to 16 bit */
return (int32_t) (int16_t) tmp;
}
/* decode CB-format shamt field
* shamt[5] = inst[12]
* shamt[4:0] = inst[6:2]
*/
static inline uint8_t c_decode_cbtype_shamt(const uint16_t insn)
{
uint8_t tmp = 0;
tmp |= (insn & CB_SHAMT_5) >> 7;
tmp |= (insn & CB_SHAMT_4_0) >> 2;
return tmp;
}
/* decode CB-format instruction immediate
* imm[8] = inst[12]
* imm[7:6] = inst[6:5]
* imm[4:3] = inst[11:10]
* imm[5] = inst[2]
* imm[2:1] = inst[4:3]
*/
static inline uint16_t c_decode_cbtype_imm(const uint16_t insn)
{
uint16_t tmp = 0;
/* ....xxxx....xxxx */
tmp |= (insn & 0b0000000000011000) >> 2;
tmp |= (insn & 0b0000110000000000) >> 7;
tmp |= (insn & 0b0000000000000100) << 3;
tmp |= (insn & 0b0000000001100000) << 1;
tmp |= (insn & 0b0001000000000000) >> 4;
/* extend to 16 bit */
for (int i = 1; i <= 8; ++i)
tmp |= (0x0100 & tmp) << i;
return tmp;
}
#endif /* RV32_HAS(EXT_C) */
/* decode I-type
* 31 20 19 15 14 12 11 7 6 0
* | imm[11:0] | rs1 | funct3 | rd | opcode |
*/
static inline void decode_itype(rv_insn_t *ir, const uint32_t insn)
{
ir->imm = decode_itype_imm(insn);
ir->rs1 = decode_rs1(insn);
ir->rd = decode_rd(insn);
}
/* decode U-type
* 31 12 11 7 6 0
* | imm[31:12] | rd | opcode |
*/
static inline void decode_utype(rv_insn_t *ir, const uint32_t insn)
{
ir->imm = decode_utype_imm(insn);
ir->rd = decode_rd(insn);
}
/* decode S-type
* 31 25 24 20 19 15 14 12 11 7 6 0
* | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode |
*/
static inline void decode_stype(rv_insn_t *ir, const uint32_t insn)
{
ir->imm = decode_stype_imm(insn);
ir->rs2 = decode_rs2(insn);
ir->rs1 = decode_rs1(insn);
}
/* decode R-type
* 31 25 24 20 19 15 14 12 11 7 6 0
* | funct7 | rs2 | rs1 | funct3 | rd | opcode |
*/
static inline void decode_rtype(rv_insn_t *ir, const uint32_t insn)
{
ir->rs2 = decode_rs2(insn);
ir->rs1 = decode_rs1(insn);
ir->rd = decode_rd(insn);
}
/* decode B-type
* 31 30 25 24 20 19 15 14 12 11 8 7 6 0
* | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |
*/
static inline void decode_btype(rv_insn_t *ir, const uint32_t insn)
{
ir->imm = decode_btype_imm(insn);
ir->rs2 = decode_rs2(insn);
ir->rs1 = decode_rs1(insn);
}
/* decode J-type
* 31 30 21 20 19 12 11 7 6 0
* | imm[20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode |
*/
static inline void decode_jtype(rv_insn_t *ir, const uint32_t insn)
{
ir->imm = decode_jtype_imm(insn);
ir->rd = decode_rd(insn);
}
#if RV32_HAS(EXT_F)
/* decode R4-type
* 31 27 26 25 24 20 19 15 14 12 11 7 6 0
* | rs3 | funct2 | rs2 | rs1 | funct3 | rd | opcode |
*/
static inline void decode_r4type(rv_insn_t *ir, const uint32_t insn)
{
ir->rd = decode_rd(insn);
ir->rs1 = decode_rs1(insn);
ir->rs2 = decode_rs2(insn);
ir->rs3 = decode_r4type_rs3(insn);
ir->rm = decode_funct3(insn);
}
#endif
/* LOAD: I-type
* 31 20 19 15 14 12 11 7 6 0
* | imm[11:0] | rs1 | funct3 | rd | opcode |
*/
static inline bool op_load(rv_insn_t *ir, const uint32_t insn)
{
/* inst imm[11:0] rs1 funct3 rd opcode
* ----+---------+---+------+--+-------
* LB imm[11:0] rs1 000 rd 0000011
* LH imm[11:0] rs1 001 rd 0000011
* LW imm[11:0] rs1 010 rd 0000011
* LD imm[11:0] rs1 011 rd 0000011
* LBU imm[11:0] rs1 100 rd 0000011
* LHU imm[11:0] rs1 101 rd 0000011
* LWU imm[11:0] rs1 110 rd 0000011
*/
/* decode I-type */
decode_itype(ir, insn);
/* dispatch from funct3 field */
switch (decode_funct3(insn)) {
case 0: /* LB: Load Byte */
ir->opcode = rv_insn_lb;
break;
case 1: /* LH: Load Halfword */
ir->opcode = rv_insn_lh;
break;
case 2: /* LW: Load Word */
ir->opcode = rv_insn_lw;
break;
case 4: /* LBU: Load Byte Unsigned */
ir->opcode = rv_insn_lbu;
break;
case 5: /* LHU: Load Halfword Unsigned */
ir->opcode = rv_insn_lhu;
break;
default: /* illegal instruction */
return false;
}
return true;
}
/* OP-IMM: I-type
* 31 20 19 15 14 12 11 7 6 0
* | imm[11:0] | rs1 | funct3 | rd | opcode |
*/
static inline bool op_op_imm(rv_insn_t *ir, const uint32_t insn)
{
/* inst imm[11:5] imm[4:0] rs1 funct3 rd opcode
* -----+---------+----------+---+------+--+-------
* ADDI imm[11:0] rs1 000 rd 0010011
* SLLI 0000000 shamt[4:0] rs1 001 rd 0010011
* SLTI imm[11:0] rs1 010 rd 0010011
* SLTIU imm[11:0] rs1 011 rd 0010011
* XORI imm[11:0] rs1 100 rd 0010011
* SLRI 0000000 shamt[4:0] rs1 101 rd 0010011
* SRAI 0100000 shamt[4:0] rs1 101 rd 0010011
* ORI imm[11:0] rs1 110 rd 0010011
* ANDI imm[11:0] rs1 111 rd 0010011
*/
/* decode I-type */
decode_itype(ir, insn);
/* nop can be implemented as "addi x0, x0, 0".
* Any integer computational instruction writing into "x0" is NOP.
*/
if (unlikely(ir->rd == rv_reg_zero)) {
ir->opcode = rv_insn_nop;
return true;
}
/* dispatch from funct3 field */
switch (decode_funct3(insn)) {
case 0: /* ADDI: Add Immediate */
ir->opcode = rv_insn_addi;
break;
case 1: /* SLLI: Shift Left Logical */
#if RV32_HAS(Zbb)
if (ir->imm == 0b011000000000) { /* clz */
ir->opcode = rv_insn_clz;
return true;
}
if (ir->imm == 0b011000000001) { /* ctz */
ir->opcode = rv_insn_ctz;
return true;
}
if (ir->imm == 0b011000000010) { /* cpop */
ir->opcode = rv_insn_cpop;
return true;
}
if (ir->imm == 0b011000000100) { /* sext.b */
ir->opcode = rv_insn_sextb;
return true;
}
if (ir->imm == 0b011000000101) { /* sext.h */
ir->opcode = rv_insn_sexth;
return true;
}
#endif
#if RV32_HAS(Zbs)
if (ir->imm >> 5 == 0b0100100) { /* bclri */
ir->opcode = rv_insn_bclri;
return true;
}
if (ir->imm >> 5 == 0b0110100) { /* binvi */
ir->opcode = rv_insn_binvi;
return true;
}
if (ir->imm >> 5 == 0b0010100) { /* bseti */
ir->opcode = rv_insn_bseti;
return true;
}
#endif
ir->opcode = rv_insn_slli;
if (unlikely(ir->imm & (1 << 5)))
return false;
break;
case 2: /* SLTI: Set on Less Than Immediate */
ir->opcode = rv_insn_slti;
break;
case 3: /* SLTIU: Set on Less Than Immediate Unsigned */
ir->opcode = rv_insn_sltiu;
break;
case 4: /* XORI: Exclusive OR Immediate */
ir->opcode = rv_insn_xori;
break;
case 5:
#if RV32_HAS(Zbb)
if (ir->imm >> 5 == 0b0110000) { /* rori */
ir->opcode = rv_insn_rori;
return true;
}
if (ir->imm == 0b001010000111) { /* orc.b */
ir->opcode = rv_insn_orcb;
return true;
}
if (ir->imm == 0b011010011000) { /* rev8 */
ir->opcode = rv_insn_rev8;
return true;
}
#endif
#if RV32_HAS(Zbs)
if (ir->imm >> 5 == 0b0100100) { /* bexti */
ir->opcode = rv_insn_bexti;
return true;
}
#endif
/* SLL, SRL, and SRA perform logical left, logical right, and
* arithmetic right shifts on the value in register rs1.
*/
ir->opcode = (ir->imm & ~0x1f)
? rv_insn_srai /* SRAI: Shift Right Arithmetic */
: rv_insn_srli; /* SRLI: Shift Right Logical */
if (unlikely(ir->imm & (1 << 5)))
return false;
break;
case 6: /* ORI: OR Immediate */
ir->opcode = rv_insn_ori;
break;
case 7: /* ANDI: AND Immediate */
ir->opcode = rv_insn_andi;
break;
default: /* illegal instruction */
return false;
}
return true;
}
/* AUIPC: U-type
* 31 12 11 7 6 0
* | imm[31:12] | rd | opcode |
*/
static inline bool op_auipc(rv_insn_t *ir, const uint32_t insn)
{
/* inst imm[31:12] rd opcode
* -----+----------+--+-------
* AUPIC imm[31:12] rd 0010111
*/
/* decode U-type */
decode_utype(ir, insn);
/* Any integer computational instruction writing into "x0" is NOP. */
if (unlikely(ir->rd == rv_reg_zero)) {
ir->opcode = rv_insn_nop;
return true;
}
ir->opcode = rv_insn_auipc;
return true;
}
/* STORE: S-type
* 31 25 24 20 19 15 14 12 11 7 6 0
* | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode |
*/
static inline bool op_store(rv_insn_t *ir, const uint32_t insn)
{
/* inst imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
* ----+---------+---+---+------+--------+-------
* SB imm[11:5] rs2 rs1 000 imm[4:0] 0100011
* SH imm[11:5] rs2 rs1 001 imm[4:0] 0100011
* SW imm[11:5] rs2 rs1 010 imm[4:0] 0100011
* SD imm[11:5] rs2 rs1 011 imm[4:0] 0100011
*/
/* decode S-type */
decode_stype(ir, insn);
/* dispatch from funct3 field */
switch (decode_funct3(insn)) {
case 0: /* SB: Store Byte */
ir->opcode = rv_insn_sb;
break;
case 1: /* SH: Store Halfword */
ir->opcode = rv_insn_sh;
break;
case 2: /* SW: Store Word */
ir->opcode = rv_insn_sw;
break;
default: /* illegal instruction */
return false;
}
return true;
}
/* OP: R-type
* 31 25 24 20 19 15 14 12 11 7 6 0
* | funct7 | rs2 | rs1 | funct3 | rd | opcode |
*/
static inline bool op_op(rv_insn_t *ir, const uint32_t insn)
{
/* inst funct7 rs2 rs1 funct3 rd opcode
* ----+-------+---+---+------+--+-------
* ADD 0000000 rs2 rs1 000 rd 0110011
* SUB 0100000 rs2 rs1 000 rd 0110011
* SLL 0000000 rs2 rs1 001 rd 0110011
* SLT 0000000 rs2 rs1 010 rd 0110011
* SLTU 0000000 rs2 rs1 011 rd 0110011
* XOR 0000000 rs2 rs1 100 rd 0110011
* SRL 0000000 rs2 rs1 101 rd 0110011
* SRA 0100000 rs2 rs1 101 rd 0110011
* OR 0000000 rs2 rs1 110 rd 0110011
* AND 0000000 rs2 rs1 111 rd 0110011
*/
/* decode R-type */
decode_rtype(ir, insn);
/* nop can be implemented as "add x0, x1, x2" */
if (unlikely(ir->rd == rv_reg_zero)) {
ir->opcode = rv_insn_nop;
return true;
}
uint8_t funct3 = decode_funct3(insn);
/* dispatch from funct7 field */
switch (decode_funct7(insn)) {
case 0b0000000:
switch (funct3) {
case 0b000: /* ADD */
ir->opcode = rv_insn_add;
break;
case 0b001: /* SLL: Shift Left Logical */
ir->opcode = rv_insn_sll;
break;
case 0b010: /* SLT: Set on Less Than */
ir->opcode = rv_insn_slt;
break;
case 0b011: /* SLTU: Set on Less Than Unsigned */
ir->opcode = rv_insn_sltu;
break;
case 0b100: /* XOR: Exclusive OR */
ir->opcode = rv_insn_xor;
break;
case 0b101: /* SRL: Shift Right Logical */
ir->opcode = rv_insn_srl;
break;
case 0b110: /* OR */
ir->opcode = rv_insn_or;
break;
case 0b111: /* AND */
ir->opcode = rv_insn_and;
break;
default: /* illegal instruction */
return false;
}
break;
#if RV32_HAS(EXT_M)
/* inst funct7 rs2 rs1 funct3 rd opcode
* ------+-------+---+---+------+--+-------
* MUL 0000001 rs2 rs1 000 rd 0110011
* MULH 0000001 rs2 rs1 001 rd 0110011
* MULHSU 0000001 rs2 rs1 010 rd 0110011
* MULHU 0000001 rs2 rs1 011 rd 0110011
* DIV 0000001 rs2 rs1 100 rd 0110011
* DIVU 0000001 rs2 rs1 101 rd 0110011
* REM 0000001 rs2 rs1 110 rd 0110011
* REMU 0000001 rs2 rs1 111 rd 0110011
*/
case 0b0000001: /* RV32M instructions */
switch (funct3) {
case 0b000: /* MUL: Multiply */
ir->opcode = rv_insn_mul;
break;
case 0b001: /* MULH: Multiply High Signed Signed */
ir->opcode = rv_insn_mulh;
break;
case 0b010: /* MULHSU: Multiply High Signed Unsigned */
ir->opcode = rv_insn_mulhsu;
break;
case 0b011: /* MULHU: Multiply High Unsigned Unsigned */
ir->opcode = rv_insn_mulhu;
break;
case 0b100: /* DIV: Divide Signed */
ir->opcode = rv_insn_div;
break;
case 0b101: /* DIVU: Divide Unsigned */
ir->opcode = rv_insn_divu;
break;
case 0b110: /* REM: Remainder Signed */
ir->opcode = rv_insn_rem;
break;
case 0b111: /* REMU: Remainder Unsigned */
ir->opcode = rv_insn_remu;
break;
default: /* illegal instruction */
return false;
}
break;
#endif /* RV32_HAS(EXT_M) */
#if RV32_HAS(Zba)
/* inst funct7 rs2 rs1 funct3 rd opcode
* ------+-------+---+---+------+--+-------
* SH1ADD 0010000 rs2 rs1 010 rd 0110011
* SH2ADD 0010000 rs2 rs1 100 rd 0110011
* SH3ADD 0010000 rs2 rs1 110 rd 0110011
*/
case 0b0010000:
switch (funct3) {
case 0b010: /* sh1add */
ir->opcode = rv_insn_sh1add;
break;
case 0b100: /* sh2add */
ir->opcode = rv_insn_sh2add;
break;
case 0b110: /* sh3add */
ir->opcode = rv_insn_sh3add;
break;
default: /* illegal instruction */
return false;
}
break;
#endif /* RV32_HAS(Zba) */
#if RV32_HAS(Zbb) || RV32_HAS(Zbc)
/* inst funct7 rs2 rs1 funct3 rd opcode
* ------+-------+---+---+------+--+-------
* MAX 0000101 rs2 rs1 110 rd 0110011
* MIN 0000101 rs2 rs1 100 rd 0110011
* MAXU 0000101 rs2 rs1 111 rd 0110011
* MINU 0000101 rs2 rs1 101 rd 0110011
* ROL 0110000 rs2 rs1 001 rd 0110011
* ROR 0110000 rs2 rs1 101 rd 0110011
*/
case 0b0000101:
switch (funct3) {
#if RV32_HAS(Zbb)
case 0b110: /* max */
ir->opcode = rv_insn_max;
break;
case 0b100: /* min */
ir->opcode = rv_insn_min;
break;
case 0b111: /* maxu */
ir->opcode = rv_insn_maxu;
break;
case 0b101: /* minu */
ir->opcode = rv_insn_minu;
break;
#endif
#if RV32_HAS(Zbc)
case 0b001: /*clmul */
ir->opcode = rv_insn_clmul;
break;
case 0b011: /*clmulh */
ir->opcode = rv_insn_clmulh;
break;
case 0b010: /*clmulr */
ir->opcode = rv_insn_clmulr;
break;
#endif
default: /* illegal instruction */
return false;
}
break;
#endif
#if RV32_HAS(Zbb)
case 0b0110000:
switch (funct3) {
case 0b001: /* rol */
ir->opcode = rv_insn_rol;
break;
case 0b101: /* ror */
ir->opcode = rv_insn_ror;
break;
default: /* illegal instruction */
return false;
}
break;
case 0b0000100:
if (unlikely(ir->rs2))
return false;
ir->opcode = rv_insn_zexth;
break;
#endif /* RV32_HAS(Zbb) */
#if RV32_HAS(Zbs)
case 0b0100100:
switch (funct3) {
case 0b001: /* bclr */
ir->opcode = rv_insn_bclr;
break;
case 0b101: /* bext */
ir->opcode = rv_insn_bext;
break;
default: /* illegal instruction */
return false;
}
break;
case 0b0110100:
if (unlikely(funct3 != 0b001))
return false;
ir->opcode = rv_insn_binv;
break;
case 0b0010100:
if (unlikely(funct3 != 0b001))
return false;
ir->opcode = rv_insn_bset;
break;
#endif /* RV32_HAS(Zbs) */
case 0b0100000:
switch (funct3) {
case 0b000: /* SUB: Substract */
ir->opcode = rv_insn_sub;
break;
case 0b101: /* SRA: Shift Right Arithmetic */
ir->opcode = rv_insn_sra;
break;
#if RV32_HAS(Zbb)
case 0b111: /* ANDN */
ir->opcode = rv_insn_andn;
break;
case 0b110: /* ORN */
ir->opcode = rv_insn_orn;
break;
case 0b100: /* XNOR */
ir->opcode = rv_insn_xnor;
break;
#endif /* RV32_HAS(Zbb) */
default: /* illegal instruction */
return false;
}
break;
default: /* illegal instruction */
return false;
}
return true;
}
/* LUI: U-type
* 31 12 11 7 6 0
* | imm[31:12] | rd | opcode |
*/
static inline bool op_lui(rv_insn_t *ir, const uint32_t insn)
{
/* inst imm[31:12] rd opcode
* ----+----------+--+-------
* LUI imm[31:12] rd 0110111
*/
/* decode U-type */
decode_utype(ir, insn);
/* Any integer computational instruction writing into "x0" is NOP. */
if (unlikely(ir->rd == rv_reg_zero)) {
ir->opcode = rv_insn_nop;
return true;
}
ir->opcode = rv_insn_lui;
return true;
}
/* Branch: B-type
* 31 30 25 24 20 19 15 14 12 11 8 7 6 0
* | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |
*/
static inline bool op_branch(rv_insn_t *ir, const uint32_t insn)
{
/* inst imm[12] imm[10:5] rs2 rs1 funct3 imm[4:1] imm[11] opcode
* ----+-------+---------+---+---+------+--------+-------+-------
* BEQ imm[12 imm[10:5] rs2 rs1 000 imm[4:1 imm[11] 1100011
* BNE imm[12 imm[10:5] rs2 rs1 001 imm[4:1 imm[11] 1100011
* BLT imm[12 imm[10:5] rs2 rs1 100 imm[4:1 imm[11] 1100011
* BGE imm[12 imm[10:5] rs2 rs1 101 imm[4:1 imm[11] 1100011
* BLTU imm[12 imm[10:5] rs2 rs1 110 imm[4:1 imm[11] 1100011
* BGEU imm[12 imm[10:5] rs2 rs1 111 imm[4:1 imm[11] 1100011
*/
/* decode B-type */
decode_btype(ir, insn);
/* dispatch from funct3 field */
switch (decode_funct3(insn)) {
case 0: /* BEQ: Branch if Equal */
ir->opcode = rv_insn_beq;
break;
case 1: /* BNE: Branch if Not Equal */
ir->opcode = rv_insn_bne;
break;
case 4: /* BLT: Branch if Less Than */
ir->opcode = rv_insn_blt;
break;
case 5: /* BGE: Branch if Greater Than */
ir->opcode = rv_insn_bge;
break;
case 6: /* BLTU: Branch if Less Than Unsigned */
ir->opcode = rv_insn_bltu;
break;
case 7: /* BGEU: Branch if Greater Than Unsigned */
ir->opcode = rv_insn_bgeu;
break;
default: /* illegal instruction */
return false;
}
return true;
}
/* JALR: I-type
* 31 20 19 15 14 12 11 7 6 0
* | imm[11:0] | rs1 | funct3 | rd | opcode |
*/
static inline bool op_jalr(rv_insn_t *ir, const uint32_t insn)
{
/* inst imm[11:0] rs1 funct3 rd opcode
* ----+---------+---+------+--+-------
* JALR imm[11:0] rs1 000 rd 1100111
*/
/* decode I-type */
decode_itype(ir, insn);
ir->opcode = rv_insn_jalr;
return true;
}
/* JAL: J-type
* 31 30 21 20 19 12 11 7 6 0
* | imm[20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode |
*/
static inline bool op_jal(rv_insn_t *ir, const uint32_t insn)
{
/* inst imm[20] imm[10:1] imm[11] imm[19:12] rd opcode
* ----+-------+---------+-------+----------+--+-------
* JALR imm[20] imm[10:1] imm[11] imm[19:12] rd 1101111
*/
/* decode J-type */
decode_jtype(ir, insn);
ir->opcode = rv_insn_jal;
return true;
}
FORCE_INLINE bool csr_is_writable(const uint32_t csr)
{
return csr < 0xc00;
}
/* SYSTEM: I-type
* 31 20 19 15 14 12 11 7 6 0
* | imm[11:0] | rs1 | funct3 | rd | opcode |
*/
static inline bool op_system(rv_insn_t *ir, const uint32_t insn)
{
/* inst imm[11:0] rs1 funct3 rd opcode
* ------+------------+-----+------+-----+-------
* ECALL 000000000000 00000 000 00000 1110011
* EBREAK 000000000001 00000 000 00000 1110011
* WFI 000100000101 00000 000 00000 1110011
* URET 000000000010 00000 000 00000 1110011
* SRET 000100000010 00000 000 00000 1110011
* HRET 001000000010 00000 000 00000 1110011
* MRET 001100000010 00000 000 00000 1110011
*/
/* inst funct7 rs2 rs1 funct3 rd opcode
* -----------+-------+---+---+------+------+-------
* SFENCE.VMA 0001001 rs2 rs1 000 00000 1110011
*/
/* decode I-type */
decode_itype(ir, insn);
/* dispatch from funct3 field */