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jit.c
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/*
* rv32emu is freely redistributable under the MIT License. See the file
* "LICENSE" for information on usage and redistribution of this file.
*/
/* This JIT implementation has undergone extensive modifications, heavily
* relying on the ubpf_jit_[x86_64|arm64].[c|h] from ubpf. The original
* ubpf_jit_[x86_64|arm64].[c|h] file served as the foundation and source of
* inspiration for adapting and tailoring it specifically for this JIT
* implementation. Therefore, credit and sincere thanks are extended to ubpf for
* their invaluable work.
*
* Reference:
* https://github.com/iovisor/ubpf/blob/main/vm/ubpf_jit_x86_64.c
* https://github.com/iovisor/ubpf/blob/main/vm/ubpf_jit_arm64.c
*/
#if !RV32_HAS(JIT)
#error "Do not manage to build this file unless you enable JIT support."
#endif
#if !defined(__x86_64__) && !defined(__aarch64__)
#error "This implementation is dedicated to x64 and arm64."
#endif
#include <assert.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/mman.h>
#include <unistd.h>
#if defined(__APPLE__)
#include <libkern/OSCacheControl.h>
#if defined(__aarch64__)
#include <pthread.h>
#endif
#endif
#include "cache.h"
#include "decode.h"
#include "io.h"
#include "jit.h"
#include "riscv.h"
#include "riscv_private.h"
#include "utils.h"
#if RV32_HAS(SYSTEM)
#include "system.h"
#endif
#define JIT_CLS_MASK 0x07
#define JIT_ALU_OP_MASK 0xf0
#define JIT_CLS_ALU 0x04
#define JIT_CLS_ALU64 0x07
#define JIT_SRC_IMM 0x00
#define JIT_SRC_REG 0x08
#define JIT_OP_MUL_IMM (JIT_CLS_ALU | JIT_SRC_IMM | 0x20)
#define JIT_OP_MUL_REG (JIT_CLS_ALU | JIT_SRC_REG | 0x20)
#define JIT_OP_DIV_IMM (JIT_CLS_ALU | JIT_SRC_IMM | 0x30)
#define JIT_OP_DIV_REG (JIT_CLS_ALU | JIT_SRC_REG | 0x30)
#define JIT_OP_MOD_IMM (JIT_CLS_ALU | JIT_SRC_IMM | 0x90)
#define JIT_OP_MOD_REG (JIT_CLS_ALU | JIT_SRC_REG | 0x90)
#define STACK_SIZE 512
#define MAX_JUMPS 1024
#define MAX_BLOCKS 8192
#define IN_JUMP_THRESHOLD 256
#if defined(__x86_64__)
/* indicate where the immediate value is in the emitted jump instruction */
#define JUMP_LOC_0 jump_loc_0 + 2
#if RV32_HAS(SYSTEM)
#define JUMP_LOC_1 jump_loc_1 + 1
#endif
/* Special values for target_pc in struct jump */
#define TARGET_PC_EXIT -1U
#define TARGET_PC_RETPOLINE -3U
enum x64_reg {
RAX,
RCX,
RDX,
RBX,
RSP,
RBP,
RIP = 5,
RSI,
RDI,
R8,
R9,
R10,
R11,
R12,
R13,
R14,
R15,
};
#elif defined(__aarch64__)
/* indicate where the immediate value is in the emitted jump instruction */
#define JUMP_LOC_0 jump_loc_0
#if RV32_HAS(SYSTEM)
#define JUMP_LOC_1 jump_loc_1
#endif
/* Special values for target_pc in struct jump */
#define TARGET_PC_EXIT ~UINT32_C(0)
#define TARGET_PC_ENTER (~UINT32_C(0) & 0x0101)
/* This is guaranteed to be an illegal A64 instruction. */
#define BAD_OPCODE ~UINT32_C(0)
enum a64_reg {
R0,
R1,
R2,
R3,
R4,
R5,
R6,
R7,
R8,
R9,
R10,
R11,
R12,
R13,
R14,
R15,
R16,
R17,
R18,
R19,
R20,
R21,
R22,
R23,
R24,
R25,
R26,
R27,
R28,
R29,
R30,
SP,
RZ = 31
};
typedef enum {
/* AddSubOpcode */
AS_ADD = 0,
AS_SUB = 2,
AS_SUBS = 3,
/* LogicalOpcode */
LOG_AND = 0x00000000U, /* 0000_0000_0000_0000_0000_0000_0000_0000 */
LOG_ORR = 0x20000000U, /* 0010_0000_0000_0000_0000_0000_0000_0000 */
LOG_ORN = 0x20200000U, /* 0010_0000_0010_0000_0000_0000_0000_0000 */
LOG_EOR = 0x40000000U, /* 0100_0000_0000_0000_0000_0000_0000_0000 */
/* LoadStoreOpcode */
LS_STRB = 0x00000000U, /* 0000_0000_0000_0000_0000_0000_0000_0000 */
LS_LDRB = 0x00400000U, /* 0000_0000_0100_0000_0000_0000_0000_0000 */
LS_LDRSBW = 0x00c00000U, /* 0000_0000_1100_0000_0000_0000_0000_0000 */
LS_STRH = 0x40000000U, /* 0100_0000_0000_0000_0000_0000_0000_0000 */
LS_LDRH = 0x40400000U, /* 0100_0000_0100_0000_0000_0000_0000_0000 */
LS_LDRSHW = 0x40c00000U, /* 0100_0000_1100_0000_0000_0000_0000_0000 */
LS_STRW = 0x80000000U, /* 1000_0000_0000_0000_0000_0000_0000_0000 */
LS_LDRW = 0x80400000U, /* 1000_0000_0100_0000_0000_0000_0000_0000 */
LS_LDRSW = 0x80800000U, /* 1000_0000_1000_0000_0000_0000_0000_0000 */
LS_STRX = 0xc0000000U, /* 1100_0000_0000_0000_0000_0000_0000_0000 */
LS_LDRX = 0xc0400000U, /* 1100_0000_0100_0000_0000_0000_0000_0000 */
/* LoadStorePairOpcode */
LSP_STPX = 0xa9000000U, /* 1010_1001_0000_0000_0000_0000_0000_0000 */
LSP_LDPX = 0xa9400000U, /* 1010_1001_0100_0000_0000_0000_0000_0000 */
/* UnconditionalBranchOpcode */
BR_BR = 0xd61f0000U, /* 1101_0110_0001_1111_0000_0000_0000_0000 */
BR_BLR = 0xd63f0000U, /* 1101_0110_0011_1111_0000_0000_0000_0000 */
BR_RET = 0xd65f0000U, /* 1101_0110_0101_1111_0000_0000_0000_0000 */
/* UnconditionalBranchImmediateOpcode */
UBR_B = 0x14000000U, /* 0001_0100_0000_0000_0000_0000_0000_0000 */
/* ConditionalBranchImmediateOpcode */
BR_Bcond = 0x54000000U,
/* DP2Opcode */
DP2_UDIV = 0x1ac00800U, /* 0001_1010_1100_0000_0000_1000_0000_0000 */
DP2_LSLV = 0x1ac02000U, /* 0001_1010_1100_0000_0010_0000_0000_0000 */
DP2_LSRV = 0x1ac02400U, /* 0001_1010_1100_0000_0010_0100_0000_0000 */
DP2_ASRV = 0x1ac02800U, /* 0001_1010_1100_0000_0010_1000_0000_0000 */
/* DP3Opcode */
DP3_MADD = 0x1b000000U, /* 0001_1011_0000_0000_0000_0000_0000_0000 */
DP3_MSUB = 0x1b008000U, /* 0001_1011_0000_0000_1000_0000_0000_0000 */
/* MoveWideOpcode */
MW_MOVN = 0x12800000U, /* 0001_0010_1000_0000_0000_0000_0000_0000 */
MW_MOVZ = 0x52800000U, /* 0101_0010_1000_0000_0000_0000_0000_0000 */
MW_MOVK = 0x72800000U, /* 0111_0010_1000_0000_0000_0000_0000_0000 */
} a64opcode_t;
enum condition {
COND_EQ,
COND_NE,
COND_HS,
COND_LO,
COND_GE = 10,
COND_LT = 11,
COND_AL = 14,
};
enum {
temp_imm_reg = R24, /* Temp register for immediate generation */
temp_div_reg = R25, /* Temp register for division results */
};
#endif
enum operand_size {
S8,
S16,
S32,
};
#if defined(__x86_64__)
/* There are two common x86-64 calling conventions, discussed at:
* https://en.wikipedia.org/wiki/X64_calling_conventions#x86-64_calling_conventions
*
* Please note: R12 is an exception and is *not* being used. Consequently, it
* is omitted from the list of non-volatile registers for both platforms,
* despite being non-volatile.
*/
#if defined(_WIN32)
static const int nonvolatile_reg[] = {RBP, RBX, RDI, RSI, R13, R14, R15};
static const int parameter_reg[] = {RCX, RDX, R8, R9};
static struct host_reg register_map[] = {
{RAX, -1, 0, 0}, {R10, -1, 0, 0}, {RDX, -1, 0, 0}, {R8, -1, 0, 0},
{R9, -1, 0, 0}, {R14, -1, 0, 0}, {R15, -1, 0, 0}, {RDI, -1, 0, 0},
{RSI, -1, 0, 0}, {RBX, -1, 0, 0}, {RBP, -1, 0, 0},
};
static int temp_reg = RCX;
#else
static const int nonvolatile_reg[] = {RBP, RBX, R13, R14, R15};
static const int parameter_reg[] = {RDI, RSI, RDX, RCX, R8, R9};
static struct host_reg register_map[] = {
{RAX, -1, 0, 0}, {RBX, -1, 0, 0}, {RDX, -1, 0, 0}, {R8, -1, 0, 0},
{R9, -1, 0, 0}, {R10, -1, 0, 0}, {R11, -1, 0, 0}, {R13, -1, 0, 0},
{R14, -1, 0, 0}, {R15, -1, 0, 0},
};
static int temp_reg = RCX;
#endif
#elif defined(__aarch64__)
/* callee_reg - this must be a multiple of two because of how we save the stack
* later on.
*/
static const int callee_reg[] = {R19, R20, R21, R22, R23, R24, R25, R26};
/* parameter_reg (Caller saved registers) */
static const int parameter_reg[] = {R0, R1, R2, R3, R4};
static int temp_reg = R8;
/* Register assignments:
* Arm64 Usage
* r0 - r4 Function parameters, caller-saved
* r6 - r8 Temp - used for storing calculated value during execution
* r19 - r23 Callee-saved registers
* r24 Temp - used for generating 32-bit immediates
* r25 Temp - used for modulous calculations
*/
static struct host_reg register_map[] = {
{R5, -1, 0, 0}, {R6, -1, 0, 0}, {R7, -1, 0, 0}, {R9, -1, 0, 0},
{R11, -1, 0, 0}, {R12, -1, 0, 0}, {R13, -1, 0, 0}, {R14, -1, 0, 0},
{R15, -1, 0, 0}, {R16, -1, 0, 0}, {R17, -1, 0, 0}, {R18, -1, 0, 0},
{R26, -1, 0, 0},
};
#endif
static const int n_host_regs =
ARRAY_SIZE(register_map); /* the number of avavliable host register */
static inline void set_dirty(int reg_idx, bool is_dirty)
{
for (int i = 0; i < n_host_regs; i++) {
/* ignore nonvolatile and parameter registers */
if (register_map[i].reg_idx != reg_idx)
continue;
register_map[i].dirty = is_dirty;
return;
}
}
static inline void offset_map_insert(struct jit_state *state, block_t *block)
{
assert(state->n_blocks < MAX_BLOCKS);
struct offset_map *map_entry = &state->offset_map[state->n_blocks++];
map_entry->pc = block->pc_start;
map_entry->offset = state->offset;
#if RV32_HAS(SYSTEM)
map_entry->satp = block->satp;
#endif
}
#if !defined(__APPLE__)
#define sys_icache_invalidate(addr, size) \
__builtin___clear_cache((char *) (addr), (char *) (addr) + (size));
#endif
static bool should_flush = false;
static void emit_bytes(struct jit_state *state, void *data, uint32_t len)
{
if (unlikely((state->offset + len) > state->size)) {
should_flush = true;
return;
}
if (unlikely(state->n_blocks == MAX_BLOCKS)) {
should_flush = true;
return;
}
#if defined(__APPLE__) && defined(__aarch64__)
pthread_jit_write_protect_np(false);
#endif
memcpy(state->buf + state->offset, data, len);
sys_icache_invalidate(state->buf + state->offset, len);
#if defined(__APPLE__) && defined(__aarch64__)
pthread_jit_write_protect_np(true);
#endif
state->offset += len;
}
#if defined(__x86_64__)
static inline void emit1(struct jit_state *state, uint8_t x)
{
emit_bytes(state, &x, sizeof(x));
}
static inline void emit4(struct jit_state *state, uint32_t x)
{
emit_bytes(state, &x, sizeof(x));
}
static inline void emit8(struct jit_state *state, uint64_t x)
{
emit_bytes(state, &x, sizeof(x));
}
static inline void emit_modrm(struct jit_state *state, int mod, int r, int m)
{
assert(!(mod & ~0xc0));
emit1(state, (mod & 0xc0) | ((r & 7) << 3) | (m & 7));
}
static inline void emit_modrm_reg2reg(struct jit_state *state, int r, int m)
{
emit_modrm(state, 0xc0, r, m);
}
static inline void emit_modrm_and_displacement(struct jit_state *state,
int r,
int m,
int32_t d)
{
if (d == 0 && (m & 7) != RBP) {
emit_modrm(state, 0x00, r, m);
} else if ((int8_t) d == d) {
emit_modrm(state, 0x40, r, m);
emit1(state, d);
} else {
emit_modrm(state, 0x80, r, m);
emit4(state, d);
}
}
static inline void emit_rex(struct jit_state *state, int w, int r, int x, int b)
{
assert(!(w & ~1));
assert(!(r & ~1));
assert(!(x & ~1));
assert(!(b & ~1));
emit1(state, 0x40 | (w << 3) | (r << 2) | (x << 1) | b);
}
/* Emit a REX prefix incorporating the top bit of both src and dst. This step is
* skipped if no bits are set.
*/
static inline void emit_basic_rex(struct jit_state *state,
int w,
int src,
int dst)
{
if (w || (src & 8) || (dst & 8))
emit_rex(state, w, !!(src & 8), 0, !!(dst & 8));
}
static inline void emit_push(struct jit_state *state, int r)
{
if (r & 8)
emit_basic_rex(state, 0, 0, r);
emit1(state, 0x50 | (r & 7));
}
static inline void emit_pop(struct jit_state *state, int r)
{
if (r & 8)
emit_basic_rex(state, 0, 0, r);
emit1(state, 0x58 | (r & 7));
}
static inline void emit_jump_target_address(struct jit_state *state,
int32_t target_pc,
uint32_t target_satp UNUSED)
{
assert(state->n_jumps < MAX_JUMPS);
struct jump *jump = &state->jumps[state->n_jumps++];
jump->offset_loc = state->offset;
jump->target_pc = target_pc;
#if RV32_HAS(SYSTEM)
jump->target_satp = target_satp;
#endif
emit4(state, 0);
}
#elif defined(__aarch64__)
static inline void emit_load_imm(struct jit_state *state,
int dst,
uint32_t imm);
static void emit_a64(struct jit_state *state, uint32_t insn)
{
assert(insn != BAD_OPCODE);
emit_bytes(state, &insn, 4);
}
/* Get the value of the size bit in most instruction encodings (bit 31). */
static inline uint32_t sz(bool is64)
{
return (is64 ? UINT32_C(1) : UINT32_C(0)) << 31;
}
/* For details on Arm instructions, users can refer to
* https://developer.arm.com/documentation/ddi0487/ha (Arm Architecture
* Reference Manual for A-profile architecture).
*/
/* [ARM-A]: C4.1.64: Add/subtract (immediate). */
static void emit_addsub_imm(struct jit_state *state,
bool is64,
a64opcode_t op,
int rd,
int rn,
uint32_t imm12)
{
const uint32_t imm_op_base = 0x11000000;
emit_a64(state, sz(is64) | (op << 29) | imm_op_base | (0 << 22) |
(imm12 << 10) | (rn << 5) | rd);
set_dirty(rd, true);
}
/* [ARM-A]: C4.1.67: Logical (shifted register). */
static void emit_logical_register(struct jit_state *state,
bool is64,
a64opcode_t op,
int rd,
int rn,
int rm)
{
emit_a64(state, sz(is64) | op | (1 << 27) | (1 << 25) | (rm << 16) |
(rn << 5) | rd);
set_dirty(rd, true);
}
/* [ARM-A]: C4.1.67: Add/subtract (shifted register). */
static inline void emit_addsub_register(struct jit_state *state,
bool is64,
a64opcode_t op,
int rd,
int rn,
int rm)
{
const uint32_t reg_op_base = 0x0b000000;
emit_a64(state,
sz(is64) | (op << 29) | reg_op_base | (rm << 16) | (rn << 5) | rd);
set_dirty(rd, true);
}
/* [ARM-A]: C4.1.64: Move wide (Immediate). */
static inline void emit_movewide_imm(struct jit_state *state,
bool is64,
int rd,
uint64_t imm)
{
/* Emit a MOVZ or MOVN followed by a sequence of MOVKs to generate the
* 64-bit constant in imm. See whether the 0x0000 or 0xffff pattern is more
* common in the immediate. This ensures we produce the fewest number of
* immediates.
*/
unsigned count0000 = is64 ? 0 : 2;
unsigned countffff = 0;
for (unsigned i = 0; i < (is64 ? 64 : 32); i += 16) {
uint64_t block = (imm >> i) & 0xffff;
if (block == 0xffff) {
++countffff;
} else if (block == 0) {
++count0000;
}
}
/* Iterate over 16-bit elements of imm, outputting an appropriate move
* instruction.
*/
bool invert = (count0000 < countffff);
a64opcode_t op = invert ? MW_MOVN : MW_MOVZ;
uint64_t skip_pattern = invert ? 0xffff : 0;
for (unsigned i = 0; i < (is64 ? 4 : 2); ++i) {
uint64_t imm16 = (imm >> (i * 16)) & 0xffff;
if (imm16 != skip_pattern) {
if (invert) {
imm16 = ~imm16;
imm16 &= 0xffff;
}
emit_a64(state, sz(is64) | op | (i << 21) | (imm16 << 5) | rd);
op = MW_MOVK;
invert = false;
}
}
/* Tidy up for the case imm = 0 or imm == -1. */
if (op != MW_MOVK)
emit_a64(state, sz(is64) | op | (0 << 21) | (0 << 5) | rd);
set_dirty(rd, true);
}
/* [ARM-A]: C4.1.66: Load/store register (unscaled immediate). */
static void emit_loadstore_imm(struct jit_state *state,
a64opcode_t op,
int rt,
int rn,
int16_t imm9)
{
const uint32_t imm_op_base = 0x38000000U;
assert(imm9 >= -256 && imm9 < 256);
imm9 &= 0x1ff;
emit_a64(state, imm_op_base | op | (imm9 << 12) | (rn << 5) | rt);
}
/* [ARM-A]: C4.1.66: Load/store register pair (offset). */
static void emit_loadstorepair_imm(struct jit_state *state,
a64opcode_t op,
int rt,
int rt2,
int rn,
int32_t imm7)
{
int32_t imm_div = ((op == LSP_STPX) || (op == LSP_LDPX)) ? 8 : 4;
assert(imm7 % imm_div == 0);
imm7 /= imm_div;
emit_a64(state, op | (imm7 << 15) | (rt2 << 10) | (rn << 5) | rt);
}
/* [ARM-A]: C4.1.65: Unconditional branch (register). */
static void emit_uncond_branch_reg(struct jit_state *state,
a64opcode_t op,
int rn)
{
emit_a64(state, op | (rn << 5));
}
/* [ARM-A]: C4.1.67: Data-processing (2 source). */
static void emit_dataproc_2source(struct jit_state *state,
bool is64,
a64opcode_t op,
int rd,
int rn,
int rm)
{
emit_a64(state, sz(is64) | op | (rm << 16) | (rn << 5) | rd);
set_dirty(rd, true);
}
#if RV32_HAS(EXT_M)
/* [ARM-A]: C4.1.67: Data-processing (3 source). */
static void emit_dataproc_3source(struct jit_state *state,
bool is64,
a64opcode_t op,
int rd,
int rn,
int rm,
int ra)
{
emit_a64(state, sz(is64) | op | (rm << 16) | (ra << 10) | (rn << 5) | rd);
set_dirty(rd, true);
}
#endif
static void update_branch_imm(struct jit_state *state,
uint32_t offset,
int32_t imm)
{
assert((imm & 3) == 0);
uint32_t insn;
imm >>= 2;
memcpy(&insn, state->buf + offset, sizeof(uint32_t));
if ((insn & 0xfe000000U) == 0x54000000U /* Conditional branch immediate. */
|| (insn & 0x7e000000U) ==
0x34000000U) { /* Compare and branch immediate. */
assert((imm >> 19) == INT64_C(-1) || (imm >> 19) == 0);
insn |= (imm & 0x7ffff) << 5;
} else if ((insn & 0x7c000000U) == 0x14000000U) {
/* Unconditional branch immediate. */
assert((imm >> 26) == INT64_C(-1) || (imm >> 26) == 0);
insn |= (imm & 0x03ffffffU) << 0;
} else {
assert(false);
insn = BAD_OPCODE;
}
#if defined(__APPLE__) && defined(__aarch64__)
pthread_jit_write_protect_np(false);
#endif
memcpy(state->buf + offset, &insn, sizeof(uint32_t));
#if defined(__APPLE__) && defined(__aarch64__)
pthread_jit_write_protect_np(true);
#endif
}
#endif
static inline void emit_jump_target_offset(struct jit_state *state,
uint32_t jump_loc_0,
uint32_t jump_state_offset)
{
assert(state->n_jumps < MAX_JUMPS);
struct jump *jump = &state->jumps[state->n_jumps++];
jump->offset_loc = jump_loc_0;
jump->target_offset = jump_state_offset;
}
static inline void emit_alu32(struct jit_state *state, int op, int src, int dst)
{
#if defined(__x86_64__)
/* The REX prefix and ModRM byte are emitted.
* The MR encoding is utilized when a choice is available. The 'src' is
* often used as an opcode extension.
*/
if (src & 8 || dst & 8)
emit_basic_rex(state, 0, src, dst);
emit1(state, op);
emit_modrm_reg2reg(state, src, dst);
set_dirty(dst, true);
#elif defined(__aarch64__)
switch (op) {
case 1: /* ADD */
emit_addsub_register(state, false, AS_ADD, dst, dst, src);
break;
case 0x29: /* SUB */
emit_addsub_register(state, false, AS_SUB, dst, dst, src);
break;
case 0x31: /* XOR */
emit_logical_register(state, false, LOG_EOR, dst, dst, src);
break;
case 9: /* OR */
emit_logical_register(state, false, LOG_ORR, dst, dst, src);
break;
case 0x21: /* AND */
emit_logical_register(state, false, LOG_AND, dst, dst, src);
break;
case 0xd3:
if (src == 4) /* SLL */
emit_dataproc_2source(state, false, DP2_LSLV, dst, dst, temp_reg);
else if (src == 5) /* SRL */
emit_dataproc_2source(state, false, DP2_LSRV, dst, dst, temp_reg);
else if (src == 7) /* SRA */
emit_dataproc_2source(state, false, DP2_ASRV, dst, dst, temp_reg);
break;
default:
__UNREACHABLE;
break;
}
#endif
}
static inline void emit_alu32_imm32(struct jit_state *state,
int op UNUSED,
int src,
int dst,
int32_t imm)
{
#if defined(__x86_64__)
/* REX prefix, ModRM byte, and 32-bit immediate */
emit_alu32(state, op, src, dst);
emit4(state, imm);
#elif defined(__aarch64__)
switch (src) {
case 0:
emit_load_imm(state, R10, imm);
emit_addsub_register(state, false, AS_ADD, dst, dst, R10);
break;
case 1:
emit_load_imm(state, R10, imm);
emit_logical_register(state, false, LOG_ORR, dst, dst, R10);
break;
case 4:
emit_load_imm(state, R10, imm);
emit_logical_register(state, false, LOG_AND, dst, dst, R10);
break;
case 6:
emit_load_imm(state, R10, imm);
emit_logical_register(state, false, LOG_EOR, dst, dst, R10);
break;
default:
__UNREACHABLE;
break;
}
#endif
}
static inline void emit_alu32_imm8(struct jit_state *state,
int op UNUSED,
int src,
int dst,
int8_t imm)
{
#if defined(__x86_64__)
/* REX prefix, ModRM byte, and 8-bit immediate */
emit_alu32(state, op, src, dst);
emit1(state, imm);
#elif defined(__aarch64__)
switch (src) {
case 4:
emit_load_imm(state, R10, imm);
emit_dataproc_2source(state, false, DP2_LSLV, dst, dst, R10);
break;
case 5:
emit_load_imm(state, R10, imm);
emit_dataproc_2source(state, false, DP2_LSRV, dst, dst, R10);
break;
case 7:
emit_load_imm(state, R10, imm);
emit_dataproc_2source(state, false, DP2_ASRV, dst, dst, R10);
break;
default:
__UNREACHABLE;
break;
}
#endif
}
static inline void emit_alu64(struct jit_state *state, int op, int src, int dst)
{
#if defined(__x86_64__)
/* The REX.W prefix and ModRM byte are emitted.
* The MR encoding is used when there is a choice. 'src' is often used as
* an opcode extension.
*/
emit_basic_rex(state, 1, src, dst);
emit1(state, op);
emit_modrm_reg2reg(state, src, dst);
set_dirty(dst, true);
#elif defined(__aarch64__)
if (op == 0x01)
emit_addsub_register(state, true, AS_ADD, dst, dst, src);
#endif
}
#if RV32_HAS(EXT_M)
static inline void emit_alu64_imm8(struct jit_state *state,
int op,
int src UNUSED,
int dst,
int8_t imm)
{
#if defined(__x86_64__)
/* REX.W prefix, ModRM byte, and 8-bit immediate */
emit_alu64(state, op, src, dst);
emit1(state, imm);
#elif defined(__aarch64__)
if (op == 0xc1) {
emit_load_imm(state, R10, imm);
emit_dataproc_2source(state, true, DP2_LSRV, dst, dst, R10);
}
#endif
}
#endif
/* Register to register mov */
static inline void emit_mov(struct jit_state *state, int src, int dst)
{
#if defined(__x86_64__)
emit_alu64(state, 0x89, src, dst);
#elif defined(__aarch64__)
emit_load_imm(state, R10, 0);
emit_addsub_register(state, false, AS_ADD, dst, src, R10);
#endif
}
#if defined(__x86_64__)
/* REX.W prefix, ModRM byte, and 32-bit immediate */
static inline void emit_alu64_imm32(struct jit_state *state,
int op,
int src,
int dst,
int32_t imm)
{
emit_alu64(state, op, src, dst);
emit4(state, imm);
}
#endif
static inline void emit_cmp_imm32(struct jit_state *state, int dst, int32_t imm)
{
#if defined(__x86_64__)
emit_alu32_imm32(state, 0x81, 7, dst, imm);
#elif defined(__aarch64__)
emit_load_imm(state, R10, imm);
emit_addsub_register(state, false, AS_SUBS, RZ, dst, R10);
#endif
}
static inline void emit_cmp32(struct jit_state *state, int src, int dst)
{
#if defined(__x86_64__)
emit_alu32(state, 0x39, src, dst);
#elif defined(__aarch64__)
emit_addsub_register(state, false, AS_SUBS, RZ, dst, src);
#endif
}
static inline void emit_jcc_offset(struct jit_state *state, int code)
{
#if defined(__x86_64__)
/* unconditional jump instruction does not have 0x0f prefix */
if (code != 0xe9)
emit1(state, 0x0f);
emit1(state, code);
emit4(state, 0);
#elif defined(__aarch64__)
switch (code) {
case 0x84: /* BEQ */
code = COND_EQ;
break;
case 0x85: /* BNE */
code = COND_NE;
break;
case 0x8c: /* BLT */
code = COND_LT;
break;
case 0x8d: /* BGE */
code = COND_GE;
break;
case 0x82: /* BLTU */
code = COND_LO;
break;
case 0x83: /* BGEU */
code = COND_HS;
break;
case 0xe9: /* AL */
code = COND_AL;
break;
default:
assert(NULL);
__UNREACHABLE;
}
emit_a64(state, BR_Bcond | (0 << 5) | code);
#endif
}
static inline void emit_load_imm(struct jit_state *state,
int dst,
uint32_t imm);
/* Load [src + offset] into dst.
*
* If the offset is non-zero, it restores the vm register to the host register
* from the stack. Otherwise, it is a `read` pseudo instruction that loading
* the [src] into destination register.
*/
static inline void emit_load(struct jit_state *state,
enum operand_size size,
int src,
int dst,
int32_t offset)
{
for (int i = 0; i < n_host_regs; i++) {
if (register_map[i].reg_idx != dst)
continue;
if (register_map[i].vm_reg_idx != 0)
continue;
/* if dst is x0, load 0x0 into host register */
emit_load_imm(state, dst, 0x0);
set_dirty(dst, true);
return;
}
#if defined(__x86_64__)
if (src & 8 || dst & 8)
emit_basic_rex(state, 0, dst, src);
if (size == S8 || size == S16) {
/* movzx */
emit1(state, 0x0f);
emit1(state, size == S8 ? 0xb6 : 0xb7);
} else if (size == S32) {
/* mov */
emit1(state, 0x8b);
} else {
assert(NULL);
__UNREACHABLE;
}
emit_modrm_and_displacement(state, dst, src, offset);
#elif defined(__aarch64__)
switch (size) {
case S8:
emit_loadstore_imm(state, LS_LDRB, dst, src, offset);
break;
case S16:
emit_loadstore_imm(state, LS_LDRH, dst, src, offset);
break;
case S32:
emit_loadstore_imm(state, LS_LDRW, dst, src, offset);
break;
default:
assert(NULL);
__UNREACHABLE;
}
#endif
set_dirty(dst, !offset);
}
static inline void emit_load_sext(struct jit_state *state,
enum operand_size size,
int src,
int dst,
int32_t offset)
{
for (int i = 0; i < n_host_regs; i++) {
if (register_map[i].reg_idx != dst)
continue;
if (register_map[i].vm_reg_idx != 0)
continue;
/* if dst is x0, load 0x0 into host register */
emit_load_imm(state, dst, 0x0);
set_dirty(dst, true);
return;
}
#if defined(__x86_64__)
if (size == S8 || size == S16) {
if (src & 8 || dst & 8)
emit_basic_rex(state, 0, dst, src);
/* movsx */
emit1(state, 0x0f);
emit1(state, size == S8 ? 0xbe : 0xbf);
} else if (size == S32) {
emit_basic_rex(state, 1, dst, src);
emit1(state, 0x63);
}
emit_modrm_and_displacement(state, dst, src, offset);
#elif defined(__aarch64__)
switch (size) {
case S8:
emit_loadstore_imm(state, LS_LDRSBW, dst, src, offset);
break;
case S16:
emit_loadstore_imm(state, LS_LDRSHW, dst, src, offset);
break;
case S32:
emit_loadstore_imm(state, LS_LDRSW, dst, src, offset);
break;
default:
__UNREACHABLE;
break;
}
#endif
set_dirty(dst, !offset);
}
/* Load 32-bit immediate into register (zero-extend) */
static inline void emit_load_imm(struct jit_state *state, int dst, uint32_t imm)
{
#if defined(__x86_64__)
if (dst & 8)
emit_basic_rex(state, 0, 0, dst);
emit1(state, 0xb8 | (dst & 7));
emit4(state, imm);
set_dirty(dst, true);
#elif defined(__aarch64__)
emit_movewide_imm(state, true, dst, imm);
#endif
}
/* Load sign-extended immediate into register */
static inline void emit_load_imm_sext(struct jit_state *state,
int dst,
int64_t imm)
{
#if defined(__x86_64__)
if ((int32_t) imm == imm)
emit_alu64_imm32(state, 0xc7, 0, dst, imm);
else {