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rv32_template.c
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/* RV32I Base Instruction Set */
/* conforming to the instructions specified in chapter 2 of the unprivileged
* specification version 20191213.
*/
/* This file establishes a low-level instruction execution abstraction layer,
* crucial for both the interpreter's instruction dispatching and the
* execution of native functions written to memory. The JIT compiler currently
* supports only x86-64 (x64) and Aarch64 (Arm64) architectures, which
* simplifies the process due to their abundant registers and register-based
* calling conventions. It effectively navigates the limitations associated
* with self-modifying code.
*
* To accommodate the specific needs of these platforms, a highly selective
* approach in practices and design is adopted. The file is designed as a
* foundational template for code generation in both the interpreter and JIT
* contexts. To facilitate this, a domain-specific language (DSL) is utilized,
* augmented by a C macro named 'RVOP'. Furthermore, a Python script is employed
* to convert code templates efficiently, enabling automatic generation of the
* JIT code generator and thus eliminating the need for repetitive manual
* coding.
*
* Example:
*
* RVOP(
* addi,
* { rv->X[ir->rd] = (int32_t) (rv->X[ir->rs1]) + ir->imm; },
* GEN({
* rald, VR0, rs1;
* map, VR1, rd;
* cond, regneq;
* mov, VR0, VR1;
* end;
* alu32imm, 32, 0x81, 0, VR1, imm;
* }))
*
* VR0, VR1, VR2 are host registers for storing calculated value
* during execution. TMP are host registers for storing temporary calculated
* value or memory address during execution. The block defined as 'GEN' is
* mapped to the generic C code used in the interpreter. The following
* instructions will be generated by JIT compiler:
* - Load X->rs1 (target field) from the rv data structure to VR0
* (destination register), if X->rs1 has been loaded to the host register, the
* host register number would be assigned to VR0.
* - Map the host register to VM register X->rd.
* - Move the register value of VR0 (X->rs1) into VR1 (X->rd) if the
* VR0 (X->rs1) is not equal to VR1 (X->rd).
* - Add imm to VR1 (X->rd)
*
* The sequence of host instructions generated during dynamic binary translation
* for the addi instruction:
* mov VR0, [memory address of (rv->X + rs1)]
* mov VR1, VR0
* add VR1, imm
*
* The parameter of x64 or arm64 instruction API
* - size: size of data
* - op: opcode
* - src: source register
* - dst: destination register
* - pc: program counter
*
* Here is the mnemonic listing for the DSL.
*
* | Mnemonic | Meaning |
* |--------------------------------+----------------------------------------|
* | alu[32|64]imm, size, op, | Do ALU operation on src and imm and |
* | src, dst, imm; | store the result into dst. |
* | alu[32|64], op, src, dst; | Do ALU operation on src and dst and |
* | | store the result into dst. |
* | ldimm, dst, imm32; | Load immediate into dst. (zero-extend) |
* | ldimms, dst, imm; | Load immediate into dst. |
* | lds, size, src, dst, | Load data of a specified size from |
* | offset; | memory and sign-extend it into the dst,|
* | | using the memory address calculated as |
* | | the sum of the src and the specified |
* | | offset. |
* | rald, dst, field | Map VM register to host register, and |
* | | load the target field from rv data |
* | | if needed. |
* | rald2, field1, field2 | Map 2 VM register to 2 host register, |
* | | and load the target fields from rv data|
* | | respectively if needed. |
* | rald2s, field1, field2 | Map 2 VM register to 2 host register, |
* | | and load the target fields from rv data|
* | | and sign-extend it respectively. |
* | map, dst, field | Map VM register to host register. |
* | ld, size, dst, member, field; | load the target field from rv data |
* | | structure to dst. |
* | st, size, src, member, field; | store src value to the target field of |
* | | rv data structure. |
* | cmp, src, dst; | compare the value between src and dst. |
* | cmpimm, src, imm; | compare the value of src and imm. |
* | jmp, pc, imm; | jump to the program counter of pc + imm|
* | jcc, op; | jump with condition. |
* | setjmpoff; | set the location of jump with condition|
* | | instruction. |
* | jmpoff; | set the jump target of jump with |
* | | condition instruction. |
* | mem; | get memory base. |
* | call, handler; | call function handler stored in rv->io |
* | exit; | exit machine code execution. |
* | mul, op, src, dst, imm; | Do mul operation on src and dst and |
* | | store the result into dst. |
* | div, op, src, dst, imm; | Do div operation on src and dst and |
* | | store the result into dst. |
* | mod, op, src, dst, imm; | Do mod operation on src and dst and |
* | | store the result into dst. |
* | cond, src; | set condition if (src) |
* | end; | set the end of condition if (src) |
* | predict; | parse the branch table of indirect |
* | | jump and search the jump target with |
* | | maximal frequency. Then, comparing |
* | | and jumping to the target if the |
* | | program counter matches. |
* | break; | In the end of a basic block, we need |
* | | to store all VM register value to rv |
* | | data, because the register allocation |
* | | is only applied on a basic block. |
*/
/* Internal */
RVOP(nop, { rv->X[rv_reg_zero] = 0; }, GEN({/* no operation */}))
/* LUI is used to build 32-bit constants and uses the U-type format. LUI
* places the U-immediate value in the top 20 bits of the destination
* register rd, filling in the lowest 12 bits with zeros. The 32-bit
* result is sign-extended to 64 bits.
*/
RVOP(
lui,
{ rv->X[ir->rd] = ir->imm; },
GEN({
map, VR0, rd;
ldimm, VR0, imm;
}))
/* AUIPC is used to build pc-relative addresses and uses the U-type format.
* AUIPC forms a 32-bit offset from the 20-bit U-immediate, filling in the
* lowest 12 bits with zeros, adds this offset to the address of the AUIPC
* instruction, then places the result in register rd.
*/
RVOP(
auipc,
{ rv->X[ir->rd] = ir->imm + PC; },
GEN({
map, VR0, rd;
ldimm, VR0, pc, imm;
}))
/* JAL: Jump and Link
* store successor instruction address into rd.
* add next J imm (offset) to pc.
*/
RVOP(
jal,
{
const uint32_t pc = PC;
/* Jump */
PC += ir->imm;
/* link with return address */
if (ir->rd)
rv->X[ir->rd] = pc + 4;
/* check instruction misaligned */
#if !RV32_HAS(EXT_C)
RV_EXC_MISALIGN_HANDLER(pc, INSN, false, 0);
#endif
struct rv_insn *taken = ir->branch_taken;
if (taken) {
#if RV32_HAS(JIT)
IIF(RV32_HAS(SYSTEM)(if (!rv->is_trapped && !reloc_enable_mmu), ))
{
IIF(RV32_HAS(SYSTEM))
(block_t *next =, ) cache_get(rv->block_cache, PC, true);
IIF(RV32_HAS(SYSTEM))(if (next->satp == rv->csr_satp), )
{
if (!set_add(&pc_set, PC))
has_loops = true;
if (cache_hot(rv->block_cache, PC))
goto end_op;
}
}
#endif
#if RV32_HAS(SYSTEM)
if (!rv->is_trapped)
#endif
{
/*
* The last_pc should only be updated when not in the trap path.
* Updating it during the trap path could lead to incorrect
* block chaining in rv_step(). Specifically, an interrupt might
* occur before locating the previous block with last_pc, and
* since __trap_handler() uses the same RVOP, the last_pc could
* be updated incorrectly during the trap path.
*
* This rule also applies to same statements elsewhere in this
* file.
*/
last_pc = PC;
MUST_TAIL return taken->impl(rv, taken, cycle, PC);
}
}
goto end_op;
},
GEN({
cond, rd;
map, VR0, rd;
ldimm, VR0, pc, 4;
end;
break;
jmp, pc, imm;
ldimm, TMP, pc, imm;
st, S32, TMP, PC;
exit;
}))
/* The branch history table records historical data pertaining to indirect jump
* targets. This functionality alleviates the need to invoke block_find() and
* incurs overhead only when the indirect jump targets are not previously
* recorded. Additionally, the C code generator can reference the branch history
* table to link he indirect jump targets.
*/
#if !RV32_HAS(JIT)
#define LOOKUP_OR_UPDATE_BRANCH_HISTORY_TABLE() \
/* \
* lookup branch history table \
* \
* When handling trap, the branch history table should not be lookup since \
* it causes return from the trap_handler. \
* \
* In addition, before relocate_enable_mmu, the block maybe retranslated, \
* thus the branch history lookup table should not be updated too. \
*/ \
IIF(RV32_HAS(GDBSTUB)(if (!rv->debug_mode), )) \
{ \
IIF(RV32_HAS(SYSTEM)(if (!rv->is_trapped && !reloc_enable_mmu), )) \
{ \
for (int i = 0; i < HISTORY_SIZE; i++) { \
if (ir->branch_table->PC[i] == PC) { \
MUST_TAIL return ir->branch_table->target[i]->impl( \
rv, ir->branch_table->target[i], cycle, PC); \
} \
} \
block_t *block = block_find(&rv->block_map, PC); \
if (block) { \
/* update branch history table */ \
ir->branch_table->PC[ir->branch_table->idx] = PC; \
ir->branch_table->target[ir->branch_table->idx] = \
block->ir_head; \
ir->branch_table->idx = \
(ir->branch_table->idx + 1) % HISTORY_SIZE; \
MUST_TAIL return block->ir_head->impl(rv, block->ir_head, \
cycle, PC); \
} \
} \
}
#else
#define LOOKUP_OR_UPDATE_BRANCH_HISTORY_TABLE() \
IIF(RV32_HAS(SYSTEM))(if (!rv->is_trapped && !reloc_enable_mmu), ) \
{ \
block_t *block = cache_get(rv->block_cache, PC, true); \
if (block) { \
for (int i = 0; i < HISTORY_SIZE; i++) { \
if (ir->branch_table->PC[i] == PC) { \
IIF(RV32_HAS(SYSTEM)) \
(if (ir->branch_table->satp[i] == rv->csr_satp), ) \
{ \
ir->branch_table->times[i]++; \
if (cache_hot(rv->block_cache, PC)) \
goto end_op; \
} \
} \
} \
/* update branch history table */ \
int min_idx = 0; \
for (int i = 0; i < HISTORY_SIZE; i++) { \
if (!ir->branch_table->times[i]) { \
min_idx = i; \
break; \
} else if (ir->branch_table->times[min_idx] > \
ir->branch_table->times[i]) { \
min_idx = i; \
} \
} \
ir->branch_table->times[min_idx] = 1; \
ir->branch_table->PC[min_idx] = PC; \
IIF(RV32_HAS(SYSTEM)) \
(ir->branch_table->satp[min_idx] = rv->csr_satp, ); \
if (cache_hot(rv->block_cache, PC)) \
goto end_op; \
MUST_TAIL return block->ir_head->impl(rv, block->ir_head, cycle, \
PC); \
} \
}
#endif
/* The indirect jump instruction JALR uses the I-type encoding. The target
* address is obtained by adding the sign-extended 12-bit I-immediate to the
* register rs1, then setting the least-significant bit of the result to zero.
* The address of the instruction following the jump (pc+4) is written to
* register rd. Register x0 can be used as the destination if the result is
* not required.
*/
RVOP(
jalr,
{
const uint32_t pc = PC;
/* jump */
PC = (rv->X[ir->rs1] + ir->imm) & ~1U;
/* link */
if (ir->rd)
rv->X[ir->rd] = pc + 4;
/* check instruction misaligned */
#if !RV32_HAS(EXT_C)
RV_EXC_MISALIGN_HANDLER(pc, INSN, false, 0);
#endif
LOOKUP_OR_UPDATE_BRANCH_HISTORY_TABLE();
#if RV32_HAS(SYSTEM)
/*
* relocate_enable_mmu is the first function called to set up the MMU.
* Inside the function, at address 0x98, an invalid PTE is accessed,
* causing a fetch page fault and trapping into the trap_handler, and
* it will not return via sret.
*
* After the jalr instruction at physical address 0xc00000b4
* (the final instruction of relocate_enable_mmu), the MMU becomes
* available.
*
* Based on this, we need to manually escape from the trap_handler after
* the jalr instruction is executed.
*/
if (!reloc_enable_mmu && reloc_enable_mmu_jalr_addr == 0xc00000b4) {
reloc_enable_mmu = true;
need_retranslate = true;
rv->is_trapped = false;
}
#endif /* RV32_HAS(SYSTEM) */
goto end_op;
},
GEN({
/* The register which stores the indirect address needs to be loaded
* first to avoid being overriden by other operation.
*/
rald, VR0, rs1;
mov, VR0, TMP;
alu32imm, 32, 0x81, 0, TMP, imm;
alu32imm, 32, 0x81, 4, TMP, ~1U;
cond, rd;
map, VR1, rd;
ldimm, VR1, pc, 4;
end;
break;
predict;
st, S32, TMP, PC;
exit;
}))
/* clang-format off */
#define BRANCH_COND(type, x, y, cond) \
(type) x cond (type) y
/* clang-format on */
#define BRANCH_FUNC(type, cond) \
IIF(RV32_HAS(EXT_C))(, const uint32_t pc = PC;); \
if (BRANCH_COND(type, rv->X[ir->rs1], rv->X[ir->rs2], cond)) { \
IIF(RV32_HAS(SYSTEM)) \
( \
{ \
if (!rv->is_trapped) { \
is_branch_taken = false; \
} \
}, \
is_branch_taken = false;); \
struct rv_insn *untaken = ir->branch_untaken; \
if (!untaken) \
goto nextop; \
IIF(RV32_HAS(JIT)) \
( \
{ \
block_t *next = cache_get(rv->block_cache, PC + 4, true); \
if (next IIF(RV32_HAS(SYSTEM))( \
&&next->satp == rv->csr_satp, )) { \
if (!set_add(&pc_set, PC + 4)) \
has_loops = true; \
if (cache_hot(rv->block_cache, PC + 4)) \
goto nextop; \
} \
}, ); \
PC += 4; \
IIF(RV32_HAS(SYSTEM)) \
( \
{ \
if (!rv->is_trapped) { \
last_pc = PC; \
MUST_TAIL return untaken->impl(rv, untaken, cycle, PC); \
} \
}, ); \
goto end_op; \
} \
IIF(RV32_HAS(SYSTEM)) \
( \
{ \
if (!rv->is_trapped) { \
is_branch_taken = true; \
} \
}, \
is_branch_taken = true;); \
PC += ir->imm; \
/* check instruction misaligned */ \
IIF(RV32_HAS(EXT_C)) \
(, RV_EXC_MISALIGN_HANDLER(pc, INSN, false, 0);); \
struct rv_insn *taken = ir->branch_taken; \
if (taken) { \
IIF(RV32_HAS(JIT)) \
( \
{ \
block_t *next = cache_get(rv->block_cache, PC, true); \
if (next IIF(RV32_HAS(SYSTEM))( \
&&next->satp == rv->csr_satp, )) { \
if (!set_add(&pc_set, PC)) \
has_loops = true; \
if (cache_hot(rv->block_cache, PC)) \
goto end_op; \
} \
}, ); \
IIF(RV32_HAS(SYSTEM)) \
( \
{ \
if (!rv->is_trapped) { \
last_pc = PC; \
MUST_TAIL return taken->impl(rv, taken, cycle, PC); \
} \
}, ); \
} \
goto end_op;
/* In RV32I and RV64I, if the branch is taken, set pc = pc + offset, where
* offset is a multiple of two; else do nothing. The offset is 13 bits long.
*
* The condition for branch taken depends on the value in mnemonic, which is
* one of:
* - "beq": src1 == src2
* - "bne": src1 != src2
* - "blt": src1 < src2 as signed integers
* - "bge": src1 >= src2 as signed integers
* - "bltu": src1 < src2 as unsigned integers
* - "bgeu": src1 >= src2 as unsigned integers
*
* On branch taken, an instruction-address-misaligned exception is generated
* if the target pc is not 4-byte aligned.
*/
/* BEQ: Branch if Equal */
RVOP(
beq,
{ BRANCH_FUNC(uint32_t, !=); },
GEN({
rald2, rs1, rs2;
cmp, VR1, VR0;
break;
setjmpoff;
jcc, 0x84;
cond, branch_untaken;
jmp, pc, 4;
end;
ldimm, TMP, pc, 4;
st, S32, TMP, PC;
exit;
jmpoff;
cond, branch_taken;
jmp, pc, imm;
end;
ldimm, TMP, pc, imm;
st, S32, TMP, PC;
exit;
}))
/* BNE: Branch if Not Equal */
RVOP(
bne,
{ BRANCH_FUNC(uint32_t, ==); },
GEN({
rald2, rs1, rs2;
cmp, VR1, VR0;
break;
setjmpoff;
jcc, 0x85;
cond, branch_untaken;
jmp, pc, 4;
end;
ldimm, TMP, pc, 4;
st, S32, TMP, PC;
exit;
jmpoff;
cond, branch_taken;
jmp, pc, imm;
end;
ldimm, TMP, pc, imm;
st, S32, TMP, PC;
exit;
}))
/* BLT: Branch if Less Than */
RVOP(
blt,
{ BRANCH_FUNC(int32_t, >=); },
GEN({
rald2, rs1, rs2;
cmp, VR1, VR0;
break;
setjmpoff;
jcc, 0x8c;
cond, branch_untaken;
jmp, pc, 4;
end;
ldimm, TMP, pc, 4;
st, S32, TMP, PC;
exit;
jmpoff;
cond, branch_taken;
jmp, pc, imm;
end;
ldimm, TMP, pc, imm;
st, S32, TMP, PC;
exit;
}))
/* BGE: Branch if Greater Than */
RVOP(
bge,
{ BRANCH_FUNC(int32_t, <); },
GEN({
rald2, rs1, rs2;
cmp, VR1, VR0;
break;
setjmpoff;
jcc, 0x8d;
cond, branch_untaken;
jmp, pc, 4;
end;
ldimm, TMP, pc, 4;
st, S32, TMP, PC;
exit;
jmpoff;
cond, branch_taken;
jmp, pc, imm;
end;
ldimm, TMP, pc, imm;
st, S32, TMP, PC;
exit;
}))
/* BLTU: Branch if Less Than Unsigned */
RVOP(
bltu,
{ BRANCH_FUNC(uint32_t, >=); },
GEN({
rald2, rs1, rs2;
cmp, VR1, VR0;
break;
setjmpoff;
jcc, 0x82;
cond, branch_untaken;
jmp, pc, 4;
end;
ldimm, TMP, pc, 4;
st, S32, TMP, PC;
exit;
jmpoff;
cond, branch_taken;
jmp, pc, imm;
end;
ldimm, TMP, pc, imm;
st, S32, TMP, PC;
exit;
}))
/* BGEU: Branch if Greater Than Unsigned */
RVOP(
bgeu,
{ BRANCH_FUNC(uint32_t, <); },
GEN({
rald2, rs1, rs2;
cmp, VR1, VR0;
break;
setjmpoff;
jcc, 0x83;
cond, branch_untaken;
jmp, pc, 4;
end;
ldimm, TMP, pc, 4;
st, S32, TMP, PC;
exit;
jmpoff;
cond, branch_taken;
jmp, pc, imm;
end;
ldimm, TMP, pc, imm;
st, S32, TMP, PC;
exit;
}))
/* There are 5 types of loads: two for byte and halfword sizes, and one for word
* size. Two instructions are required for byte and halfword loads because they
* can be either zero-extended or sign-extended to fill the register. However,
* for word-sized loads, an entire register's worth of data is read from memory,
* and no extension is needed.
*/
/* LB: Load Byte */
RVOP(
lb,
{
uint32_t addr = rv->X[ir->rs1] + ir->imm;
rv->X[ir->rd] = sign_extend_b(rv->io.mem_read_b(rv, addr));
},
GEN({
mem;
rald, VR0, rs1;
ldimms, TMP, mem;
alu64, 0x01, VR0, TMP;
map, VR1, rd;
lds, S8, TMP, VR1, 0;
}))
/* LH: Load Halfword */
RVOP(
lh,
{
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
RV_EXC_MISALIGN_HANDLER(1, LOAD, false, 1);
rv->X[ir->rd] = sign_extend_h(rv->io.mem_read_s(rv, addr));
},
GEN({
mem;
rald, VR0, rs1;
ldimms, TMP, mem;
alu64, 0x01, VR0, TMP;
map, VR1, rd;
lds, S16, TMP, VR1, 0;
}))
/* LW: Load Word */
RVOP(
lw,
{
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
RV_EXC_MISALIGN_HANDLER(3, LOAD, false, 1);
rv->X[ir->rd] = rv->io.mem_read_w(rv, addr);
},
GEN({
mem;
rald, VR0, rs1;
ldimms, TMP, mem;
alu64, 0x01, VR0, TMP;
map, VR1, rd;
ld, S32, TMP, VR1, 0;
}))
/* LBU: Load Byte Unsigned */
RVOP(
lbu,
{
uint32_t addr = rv->X[ir->rs1] + ir->imm;
rv->X[ir->rd] = rv->io.mem_read_b(rv, addr);
},
GEN({
mem;
rald, VR0, rs1;
ldimms, TMP, mem;
alu64, 0x01, VR0, TMP;
map, VR1, rd;
ld, S8, TMP, VR1, 0;
}))
/* LHU: Load Halfword Unsigned */
RVOP(
lhu,
{
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
RV_EXC_MISALIGN_HANDLER(1, LOAD, false, 1);
rv->X[ir->rd] = rv->io.mem_read_s(rv, addr);
},
GEN({
mem;
rald, VR0, rs1;
ldimms, TMP, mem;
alu64, 0x01, VR0, TMP;
map, VR1, rd;
ld, S16, TMP, VR1, 0;
}))
/* There are 3 types of stores: byte, halfword, and word-sized. Unlike loads,
* there are no signed or unsigned variants, as stores to memory write exactly
* the number of bytes specified, and there is no sign or zero extension
* involved.
*/
/* SB: Store Byte */
RVOP(
sb,
{
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
rv->io.mem_write_b(rv, addr, rv->X[ir->rs2]);
},
GEN({
mem;
rald, VR0, rs1;
ldimms, TMP, mem;
alu64, 0x01, VR0, TMP;
rald, VR1, rs2;
st, S8, VR1, TMP, 0;
}))
/* SH: Store Halfword */
RVOP(
sh,
{
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
RV_EXC_MISALIGN_HANDLER(1, STORE, false, 1);
rv->io.mem_write_s(rv, addr, rv->X[ir->rs2]);
},
GEN({
mem;
rald, VR0, rs1;
ldimms, TMP, mem;
alu64, 0x01, VR0, TMP;
rald, VR1, rs2;
st, S16, VR1, TMP, 0;
}))
/* SW: Store Word */
RVOP(
sw,
{
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
RV_EXC_MISALIGN_HANDLER(3, STORE, false, 1);
rv->io.mem_write_w(rv, addr, rv->X[ir->rs2]);
},
GEN({
mem;
rald, VR0, rs1;
ldimms, TMP, mem;
alu64, 0x01, VR0, TMP;
rald, VR1, rs2;
st, S32, VR1, TMP, 0;
}))
/* ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic
* overflow is ignored and the result is simply the low XLEN bits of the
* result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler
* pseudo-instruction.
*/
RVOP(
addi,
{ rv->X[ir->rd] = rv->X[ir->rs1] + ir->imm; },
GEN({
rald, VR0, rs1;
map, VR1, rd;
cond, regneq;
mov, VR0, VR1;
end;
alu32imm, 32, 0x81, 0, VR1, imm;
}))
/* SLTI place the value 1 in register rd if register rs1 is less than the
* signextended immediate when both are treated as signed numbers, else 0 is
* written to rd.
*/
RVOP(
slti,
{ rv->X[ir->rd] = ((int32_t) (rv->X[ir->rs1]) < ir->imm) ? 1 : 0; },
GEN({
rald, VR0, rs1;
cmpimm, VR0, imm;
map, VR1, rd;
ldimm, VR1, 1;
setjmpoff;
jcc, 0x8c;
ldimm, VR1, 0;
jmpoff;
}))
/* SLTIU places the value 1 in register rd if register rs1 is less than the
* immediate when both are treated as unsigned numbers, else 0 is written to rd.
*/
RVOP(
sltiu,
{ rv->X[ir->rd] = (rv->X[ir->rs1] < (uint32_t) ir->imm) ? 1 : 0; },
GEN({
rald, VR0, rs1;
cmpimm, VR0, imm;
map, VR1, rd;
ldimm, VR1, 1;
setjmpoff;
jcc, 0x82;
ldimm, VR1, 0;
jmpoff;
}))
/* XORI: Exclusive OR Immediate */
RVOP(
xori,
{ rv->X[ir->rd] = rv->X[ir->rs1] ^ ir->imm; },
GEN({
rald, VR0, rs1;
map, VR1, rd;
cond, regneq;
mov, VR0, VR1;
end;
alu32imm, 32, 0x81, 6, VR1, imm;
}))
/* ORI: OR Immediate */
RVOP(
ori,
{ rv->X[ir->rd] = rv->X[ir->rs1] | ir->imm; },
GEN({
rald, VR0, rs1;
map, VR1, rd;
cond, regneq;
mov, VR0, VR1;
end;
alu32imm, 32, 0x81, 1, VR1, imm;
}))
/* ANDI performs bitwise AND on register rs1 and the sign-extended 12-bit
* immediate and place the result in rd.
*/
RVOP(
andi,
{ rv->X[ir->rd] = rv->X[ir->rs1] & ir->imm; },
GEN({
rald, VR0, rs1;
map, VR1, rd;
cond, regneq;
mov, VR0, VR1;
end;
alu32imm, 32, 0x81, 4, VR1, imm;
}))
FORCE_INLINE void shift_func(riscv_t *rv, const rv_insn_t *ir)
{
switch (ir->opcode) {
case rv_insn_slli:
rv->X[ir->rd] = rv->X[ir->rs1] << (ir->imm & 0x1f);
break;
case rv_insn_srli:
rv->X[ir->rd] = rv->X[ir->rs1] >> (ir->imm & 0x1f);
break;
case rv_insn_srai:
rv->X[ir->rd] = ((int32_t) rv->X[ir->rs1]) >> (ir->imm & 0x1f);
break;
default:
__UNREACHABLE;
break;
}
};
/* SLLI performs logical left shift on the value in register rs1 by the shift
* amount held in the lower 5 bits of the immediate.
*/
RVOP(
slli,
{ shift_func(rv, ir); },
GEN({
rald, VR0, rs1;
map, VR1, rd;
cond, regneq;
mov, VR0, VR1;
end;
alu32imm, 8, 0xc1, 4, VR1, imm, 0x1f;
}))
/* SRLI performs logical right shift on the value in register rs1 by the shift
* amount held in the lower 5 bits of the immediate.
*/
RVOP(
srli,
{ shift_func(rv, ir); },
GEN({
rald, VR0, rs1;
map, VR1, rd;
cond, regneq;
mov, VR0, VR1;
end;
alu32imm, 8, 0xc1, 5, VR1, imm, 0x1f;
}))
/* SRAI performs arithmetic right shift on the value in register rs1 by the
* shift amount held in the lower 5 bits of the immediate.
*/
RVOP(
srai,
{ shift_func(rv, ir); },
GEN({
rald, VR0, rs1;
map, VR1, rd;
cond, regneq;
mov, VR0, VR1;
end;
alu32imm, 8, 0xc1, 7, VR1, imm, 0x1f;
}))
/* ADD */
RVOP(
add,
{ rv->X[ir->rd] = rv->X[ir->rs1] + rv->X[ir->rs2]; },
GEN({
rald2, rs1, rs2;
map, VR2, rd;
mov, VR1, TMP;
mov, VR0, VR2;
alu32, 0x01, TMP, VR2;
}))
/* SUB: Subtract */
RVOP(
sub,
{ rv->X[ir->rd] = rv->X[ir->rs1] - rv->X[ir->rs2]; },
GEN({
rald2, rs1, rs2;
map, VR2, rd;
mov, VR1, TMP;
mov, VR0, VR2;
alu32, 0x29, TMP, VR2;
}))
/* SLL: Shift Left Logical */
RVOP(
sll,
{ rv->X[ir->rd] = rv->X[ir->rs1] << (rv->X[ir->rs2] & 0x1f); },
GEN({
rald2, rs1, rs2;
map, VR2, rd;
mov, VR1, TMP;
mov, VR0, VR2;
alu32imm, 32, 0x81, 4, TMP, 0x1f;
alu32, 0xd3, 4, VR2;
}))
/* SLT: Set on Less Than */
RVOP(
slt,
{
rv->X[ir->rd] =
((int32_t) (rv->X[ir->rs1]) < (int32_t) (rv->X[ir->rs2])) ? 1 : 0;
},
GEN({
rald2, rs1, rs2;
map, VR2, rd;
cmp, VR1, VR0;
ldimm, VR2, 1;
setjmpoff;
jcc, 0x8c;
ldimm, VR2, 0;
jmpoff;
}))
/* SLTU: Set on Less Than Unsigned */
RVOP(
sltu,
{ rv->X[ir->rd] = (rv->X[ir->rs1] < rv->X[ir->rs2]) ? 1 : 0; },
GEN({
rald2, rs1, rs2;
map, VR2, rd;
cmp, VR1, VR0;
ldimm, VR2, 1;
setjmpoff;
jcc, 0x82;
ldimm, VR2, 0;
jmpoff;
}))
/* XOR: Exclusive OR */
RVOP(
xor,
{
rv->X[ir->rd] = rv->X[ir->rs1] ^ rv->X[ir->rs2];
},
GEN({
rald2, rs1, rs2;
map, VR2, rd;
mov, VR1, TMP;
mov, VR0, VR2;
alu32, 0x31, TMP, VR2;
}))
/* SRL: Shift Right Logical */
RVOP(
srl,
{ rv->X[ir->rd] = rv->X[ir->rs1] >> (rv->X[ir->rs2] & 0x1f); },
GEN({
rald2, rs1, rs2;
map, VR2, rd;
mov, VR1, TMP;