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Issues list

Improve support for contant generators enhancement Feature enhancement VPR VPR FPGA Placement & Routing Tool
#163 opened Nov 4, 2016 by kmurray
5
LUT input pin swapability VPR VPR FPGA Placement & Routing Tool
#157 opened Sep 16, 2016 by berbagci
4
Always statement to unpack array enhancement Feature enhancement Odin AST Odin II Logic Synthesis Tool: AST related phase (folding, optimization, scope, unrolling)) Odin Parser Odin II Logic Synthesis Tool: Verilog Preproc and Parser related Odin Odin II Logic Synthesis Tool: Unsorted item
#110 opened Dec 18, 2015 by KBragin
@KennethKent
1
Odin inserts undriven signals in netlist bug Incorrect behaviour Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Odin II Logic Synthesis Tool: Unsorted item
#96 opened Jun 26, 2015 by kmurray
@KennethKent
3
"driver defined twice" (rc4) bug Incorrect behaviour Odin AST Odin II Logic Synthesis Tool: AST related phase (folding, optimization, scope, unrolling)) Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Odin II Logic Synthesis Tool: Unsorted item
#89 opened Jun 26, 2015 by kmurray
@KennethKent
1
Odin Big Endian support enhancement Feature enhancement Odin AST Odin II Logic Synthesis Tool: AST related phase (folding, optimization, scope, unrolling)) Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Odin II Logic Synthesis Tool: Unsorted item
#79 opened Jun 26, 2015 by kmurray
@KennethKent
1
parse_vtr_flow.pl bug Incorrect behaviour VTR Flow VTR Design Flow (scripts/benchmarks/architectures)
#67 opened Jun 26, 2015 by kmurray
@kmurray @jgoeders
1
Enable STDOUT output for run_vtr_flow.pl bug Incorrect behaviour VTR Flow VTR Design Flow (scripts/benchmarks/architectures)
#63 opened Jun 26, 2015 by kmurray
@kmurray @jgoeders
1
abc crashes if genlib library is in a read-only directory and no super is available ABC ABC Logic Optimization & Technology Mapping Tool bug Incorrect behaviour
#58 opened Jun 26, 2015 by kmurray
@kmurray
ODIN-II generates more LUTs with adder bug Incorrect behaviour Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Tech.Mapping Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic Odin Odin II Logic Synthesis Tool: Unsorted item
#46 opened Jun 26, 2015 by kmurray
@KennethKent
1
run_vtr_task script bug Incorrect behaviour VTR Flow VTR Design Flow (scripts/benchmarks/architectures)
#43 opened Jun 26, 2015 by kmurray
@kmurray @jgoeders
1
Carry-chain bug bug Incorrect behaviour VPR VPR FPGA Placement & Routing Tool
#41 opened Jun 26, 2015 by kmurray
@kmurray
Cluster-hopping enhancement Feature enhancement VPR VPR FPGA Placement & Routing Tool
#33 opened Jun 26, 2015 by kmurray
@kmurray
Need better error checking for repeat pins bug Incorrect behaviour libarchfpga Library for handling FPGA Architecture descriptions
#32 opened Jun 26, 2015 by kmurray
@kmurray
1
The same molecules with the same logical blocks being packed up to three times enhancement Feature enhancement VPR VPR FPGA Placement & Routing Tool
#25 opened Jun 26, 2015 by kmurray
@kmurray
6
run_vtr_flow.pl error reporting is vague bug Incorrect behaviour VTR Flow VTR Design Flow (scripts/benchmarks/architectures)
#19 opened Jun 26, 2015 by kmurray
@kmurray @jgoeders
7
ProTip! Exclude everything labeled bug with -label:bug.