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Issues list

VTR flow library documentation is just a skeleton -- should fill in VTR Flow VTR Design Flow (scripts/benchmarks/architectures)
#2059 opened Jun 9, 2022 by vaughnbetz
@jgoeders
👍 2
[VPR] Allow for constant generators within the PB types
#1956 opened Jan 20, 2022 by acomodi
👍 2
libvtrcapnproto doesn't follow file symlinks
#1690 opened Mar 19, 2021 by mkurc-ant
👍 2
[AP] Prepacker Called Twice in AP Flow
#2950 opened Mar 24, 2025 by amin1377
@AlexandreSinger
1 👍 1
Documentation has deprecated information on VTR pre-synthetized benchmark
#2142 opened Aug 24, 2022 by gaialucas
👍 1
Build fails due to errors in Hashable.cpp
#1788 opened Jun 24, 2021 by siddhpant
3 👍 1
--graphics command doesn't seem to work
#2001 opened Mar 19, 2022 by sildipankar
1 👍 1
Error executing run_vtr_flow with -start yosys
#2152 opened Sep 5, 2022 by ept221
2 👍 1
Need better error checking for repeat pins bug Incorrect behaviour libarchfpga Library for handling FPGA Architecture descriptions
#32 opened Jun 26, 2015 by kmurray
@kmurray
1
Carry-chain bug bug Incorrect behaviour VPR VPR FPGA Placement & Routing Tool
#41 opened Jun 26, 2015 by kmurray
@kmurray
run_vtr_task script bug Incorrect behaviour VTR Flow VTR Design Flow (scripts/benchmarks/architectures)
#43 opened Jun 26, 2015 by kmurray
@kmurray @jgoeders
1
abc crashes if genlib library is in a read-only directory and no super is available ABC ABC Logic Optimization & Technology Mapping Tool bug Incorrect behaviour
#58 opened Jun 26, 2015 by kmurray
@kmurray
Enable STDOUT output for run_vtr_flow.pl bug Incorrect behaviour VTR Flow VTR Design Flow (scripts/benchmarks/architectures)
#63 opened Jun 26, 2015 by kmurray
@kmurray @jgoeders
1
Odin Big Endian support enhancement Feature enhancement Odin AST Odin II Logic Synthesis Tool: AST related phase (folding, optimization, scope, unrolling)) Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Odin II Logic Synthesis Tool: Unsorted item
#79 opened Jun 26, 2015 by kmurray
@KennethKent
1
"driver defined twice" (rc4) bug Incorrect behaviour Odin AST Odin II Logic Synthesis Tool: AST related phase (folding, optimization, scope, unrolling)) Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Odin II Logic Synthesis Tool: Unsorted item
#89 opened Jun 26, 2015 by kmurray
@KennethKent
1
Odin inserts undriven signals in netlist bug Incorrect behaviour Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Odin II Logic Synthesis Tool: Unsorted item
#96 opened Jun 26, 2015 by kmurray
@KennethKent
3
LUT input pin swapability VPR VPR FPGA Placement & Routing Tool
#157 opened Sep 16, 2016 by berbagci
4
Direct Inter-block Connections
#240 opened Sep 27, 2017 by pgaraccio
1
CLB pin mismatch between .net and .route files
#241 opened Oct 11, 2017 by sgupta020
1
Icestorm Inter-operability
#245 opened Nov 21, 2017 by mithro
5
Strip all trailing whitespace in files
#250 opened Nov 25, 2017 by mithro
Specifying a subset of pins in a pin location and causes a segfault
#258 opened Dec 5, 2017 by mithro
5
Add tags for the vtr release versions
#259 opened Dec 5, 2017 by mithro
3
Not able to install vtr on mac OS X
#263 opened Dec 9, 2017 by manikjindal91
3
Always statement to unpack array enhancement Feature enhancement Odin AST Odin II Logic Synthesis Tool: AST related phase (folding, optimization, scope, unrolling)) Odin Parser Odin II Logic Synthesis Tool: Verilog Preproc and Parser related Odin Odin II Logic Synthesis Tool: Unsorted item
#110 opened Dec 18, 2015 by KBragin
@KennethKent
1
ProTip! no:milestone will show everything without a milestone.