Welcome to my GitHub profile! I'm Sabry, a passionate Hardware Verification Engineer and IC Design Enthusiast with a strong passion for Electronic Design Automation (EDA). Below you'll find more about me, my skills, and the exciting projects I’m working on.

I’m a Junior Engineer at Si-Vision with a strong background in Digital Verification, RTL Design, and EDA development. My expertise spans building and verifying complex digital systems, with a keen interest in the intersection of EDA, AI, and VLSI Design.

I also have a solid background in software development and embedded systems. Additionally, I have experience in game development using Unity3D and C#, and as a Flutter developer.

One of my major accomplishments is the development of ART (Automated RTL and Testbench), an innovative EDA tool that transforms traditional approaches to RTL design and verification. ART accelerates UVM testbench generation, FSM design, and System Verilog Assertions creation by leveraging Natural Language Processing (NLP) and large language models. The UVM part of ART was published as a paper in the IEEE International Conference on Microelectronics (ICM). You can check out the paper here .

I was an Embedded Member at Cairo Uni Racing Team, participating in designing and implementing the entire embedded system in the EV racing vehicle. The following year, I became the Embedded Communication Sub-team Head, leading the communication team to build the car's communication system. I also developed a software solution—CURT-CUBE—to address integration challenges between other sub-teams.

Here’s a walkthrough video of the ART Tool, which demonstrates its key features:

• RTL Design: Knowledge in building RISC-V processors and ASIC design
• Verification: UVM-based verification for RTL designs
• EDA Development: Passionate about EDA tools and their application in hardware verification

• ART (Automated RTL and Testbench): Developed a tool to automate the generation of UVM testbenches, System Verilog Assertions, FSM designs, and top module connections. Built with state-of-the-art LLMs, a Verilog parser, and custom GUIs using PyQt.
• Text Classification Model: Trained models to classify Natural Language Assertions and translate them into System Verilog Assertions (SVA).
• Custom GUI Development: Designed intuitive user interfaces like Schematic (Block Diagram) Editor, FSM Editor, and UVM Configurator.

• Languages: Verilog/SystemVerilog, C/C++, Python, MATLAB
• Frameworks: TensorFlow, PyTorch (for ML/DL in EDA)
• EDA Tools: Synopsys, Cadence, Mentor Graphics
• Version Control: Git, Perforce

ART is an EDA tool that transforms the RTL design and verification process by automating the generation of UVM testbenches, System Verilog Assertions, and FSM designs. Key features include:

• Schematic Editor & Code Generator
• FSM Editor & Code Generator
• UVM Configurator & Generator
• Text Classification Model for Natural Language Assertions
• NLA to SVA Translation

The tool also includes a custom PyQt user interface for easy interaction with these features.

Successfully built a RISC-V processor and integrated it into a System-on-Chip (SoC) environment, and the next step is to verify it using UVM methodology.

I am currently a Junior Engineer in Digital Verification at Si-Vision, where I work on cutting-edge verification methodologies to ensure the reliability and performance of complex digital designs.

• Advanced techniques in digital verification methodologies and System on Chip (SoC) design
• Exploring the use of AI/ML in EDA tools and hardware design optimization

Thanks for visiting my profile! Feel free to explore my repositories and reach out if you’re interested in collaboration or have any questions.