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A tool for compression of lookup tables and generation of their hardware files in Verilog for RTL designs

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ollycassidy13/ReducedLUT

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A tool for compression of lookup tables and generation of their hardware files in Verilog for RTL designs

Topics

compression fpga neural-network rtl verilog hardware-acceleration lookup-table ip-generation rtl-generation table-size-reduction hardware-ip

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ReducedLUT Latest
Dec 16, 2024
+ 1 release

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