Trending

See what the GitHub community is most excited about today.

alexforencich / verilog-pcie

Verilog PCI express components

Verilog 1,336 344 Built by

10 stars today

The-OpenROAD-Project / OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Verilog 439 354 Built by

0 stars today

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,996 668 Built by

2 stars today

corundum / corundum

Open source FPGA-based NIC and platform for in-network compute

Verilog 1,903 460 Built by

2 stars today

alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

Verilog 2,590 763 Built by

2 stars today

nvdla / hw

RTL, Cmodel, and testbench for NVDLA

Verilog 1,894 598 Built by

2 stars today

analogdevicesinc / hdl

HDL libraries and projects

Verilog 1,664 1,569 Built by

0 stars today

YosysHQ / picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,522 828 Built by

3 stars today