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Pull requests: llvm/circt
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[circt-verilog] Add updated LLHD passes to the pipeline
ImportVerilog
#8579
opened Jun 18, 2025 by
fabianschuiki
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[FIRRTL] Improve canonicalization patterns for variadic cat and reduction operations
#8578
opened Jun 18, 2025 by
uenoku
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[MooreToCore] Lower exponentiation to math.ipowi (PowSOpConversion)
#8574
opened Jun 17, 2025 by
liamslj13
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[ImportVerilog] Support packed structs in
inside
operator
#8545
opened Jun 8, 2025 by
AnnuCode
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[CMake] Allow Python discovery from virtual environment
#8520
opened May 30, 2025 by
hamidelmaazouz
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[SharedResourcesProblem] [Simplex Scheduler] Simplex scheduler deals with multiple resource constraints
#8480
opened May 13, 2025 by
jiahanxie353
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[SCFToCalyx] Modify top-level function in place and propagate external memory allocations
#8446
opened Apr 25, 2025 by
jiahanxie353
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[ImportVerilog] Convert the unpacked array to a simple bit vector
#8392
opened Apr 4, 2025 by
AnnuCode
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When replacing a register with its reset value, attempt width coercion
FIRRTL
Involving the `firrtl` dialect
#8379
opened Apr 1, 2025 by
rwy7
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Add a few mux-of-const and reg-of-and/or canonicalizers.
FIRRTL
Involving the `firrtl` dialect
#8307
opened Mar 7, 2025 by
rwy7
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[circt-verilog-lsp] Add inlay hints support for Verilog LSP server
#8303
opened Mar 6, 2025 by
uenoku
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[circt-verilog-lsp][vscode] Add initial VS Code extension configuration for CIRCT Verilog LSP
#8281
opened Feb 27, 2025 by
uenoku
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[circt-verilog-lsp] Add definition and reference providers
#8280
opened Feb 27, 2025 by
uenoku
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[ImportVerilog] add unpacked array concatenation
Moore
#8270
opened Feb 24, 2025 by
chenbo-again
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