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0034-Xtensa-Implement-Xtensa-features-and-operations.patch
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0034-Xtensa-Implement-Xtensa-features-and-operations.patch
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From 7e6e866288b52c0b65bf3a6a55f8ec0182c5466f Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov@espressif.com>
Date: Wed, 5 Apr 2023 00:58:52 +0300
Subject: [PATCH 034/158] [Xtensa] Implement Xtensa features and operations.
Implement Exception, HighPriInterrupts, Coprocessor, Interrupt,
RelocatableVector, TimerInt, PRID, RegionProtection and MiscSR
features. Implement instructions for Exception, Interrupt and
RegionProtection features with tests.
---
.../Disassembler/XtensaDisassembler.cpp | 52 +++++++---
llvm/lib/Target/Xtensa/Xtensa.td | 46 +++++++++
llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 77 +++++++++++++++
llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 94 ++++++++++++++++++-
llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 9 ++
llvm/lib/Target/Xtensa/XtensaSubtarget.h | 45 +++++++++
llvm/test/MC/Xtensa/xtensa-valid-exc.s | 21 +++++
llvm/test/MC/Xtensa/xtensa-valid-int.s | 18 ++++
llvm/test/MC/Xtensa/xtensa-valid-regprotect.s | 14 +++
9 files changed, 356 insertions(+), 20 deletions(-)
create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-exc.s
create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-int.s
create mode 100644 llvm/test/MC/Xtensa/xtensa-valid-regprotect.s
diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
index 1f54c9549069..3cac05d74d82 100644
--- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
+++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -148,19 +148,40 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
}
static const unsigned SRDecoderTable[] = {
- Xtensa::LBEG, 0, Xtensa::LEND, 1,
- Xtensa::LCOUNT, 2, Xtensa::SAR, 3,
- Xtensa::BREG, 4, Xtensa::LITBASE, 5,
- Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
- Xtensa::M0, 32, Xtensa::M1, 33,
- Xtensa::M2, 34, Xtensa::M3, 35,
- Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73,
- Xtensa::IBREAKENABLE, 96, Xtensa::MEMCTL, 97,
- Xtensa::ATOMCTL, 99, Xtensa::IBREAKA0, 128,
- Xtensa::IBREAKA1, 129, Xtensa::DBREAKA0, 144,
- Xtensa::DBREAKA1, 145, Xtensa::DBREAKC0, 160,
- Xtensa::DBREAKC1, 161, Xtensa::DEBUGCAUSE, 233,
- Xtensa::ICOUNT, 236, Xtensa::ICOUNTLEVEL, 237};
+ Xtensa::LBEG, 0, Xtensa::LEND, 1,
+ Xtensa::LCOUNT, 2, Xtensa::SAR, 3,
+ Xtensa::BREG, 4, Xtensa::LITBASE, 5,
+ Xtensa::SCOMPARE1, 12, Xtensa::ACCLO, 16,
+ Xtensa::ACCHI, 17, Xtensa::M0, 32,
+ Xtensa::M1, 33, Xtensa::M2, 34,
+ Xtensa::M3, 35, Xtensa::WINDOWBASE, 72,
+ Xtensa::WINDOWSTART, 73, Xtensa::IBREAKENABLE, 96,
+ Xtensa::MEMCTL, 97, Xtensa::ATOMCTL, 99,
+ Xtensa::DDR, 104, Xtensa::IBREAKA0, 128,
+ Xtensa::IBREAKA1, 129, Xtensa::DBREAKA0, 144,
+ Xtensa::DBREAKA1, 145, Xtensa::DBREAKC0, 160,
+ Xtensa::DBREAKC1, 161, Xtensa::CONFIGID0, 176,
+ Xtensa::EPC1, 177, Xtensa::EPC2, 178,
+ Xtensa::EPC3, 179, Xtensa::EPC4, 180,
+ Xtensa::EPC5, 181, Xtensa::EPC6, 182,
+ Xtensa::EPC7, 183, Xtensa::DEPC, 192,
+ Xtensa::EPS2, 194, Xtensa::EPS3, 195,
+ Xtensa::EPS4, 196, Xtensa::EPS5, 197,
+ Xtensa::EPS6, 198, Xtensa::EPS7, 199,
+ Xtensa::CONFIGID1, 208, Xtensa::EXCSAVE1, 209,
+ Xtensa::EXCSAVE2, 210, Xtensa::EXCSAVE3, 211,
+ Xtensa::EXCSAVE4, 212, Xtensa::EXCSAVE5, 213,
+ Xtensa::EXCSAVE6, 214, Xtensa::EXCSAVE7, 215,
+ Xtensa::CPENABLE, 224, Xtensa::INTSET, 226,
+ Xtensa::INTCLEAR, 227, Xtensa::INTENABLE, 228,
+ Xtensa::PS, 230, Xtensa::VECBASE, 231,
+ Xtensa::EXCCAUSE, 232, Xtensa::DEBUGCAUSE, 233,
+ Xtensa::CCOUNT, 234, Xtensa::PRID, 235,
+ Xtensa::ICOUNT, 236, Xtensa::ICOUNTLEVEL, 237,
+ Xtensa::EXCVADDR, 238, Xtensa::CCOMPARE0, 240,
+ Xtensa::CCOMPARE1, 241, Xtensa::CCOMPARE2, 242,
+ Xtensa::MISC0, 244, Xtensa::MISC1, 245,
+ Xtensa::MISC2, 246, Xtensa::MISC3, 247};
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
@@ -180,8 +201,9 @@ static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
}
static const unsigned URDecoderTable[] = {
- Xtensa::THREADPTR, 231, Xtensa::FCR, 232, Xtensa::FSR, 233,
- Xtensa::F64R_LO, 234, Xtensa::F64R_HI, 235, Xtensa::F64S, 236};
+ Xtensa::EXPSTATE, 230, Xtensa::THREADPTR, 231, Xtensa::FCR, 232,
+ Xtensa::FSR, 233, Xtensa::F64R_LO, 234, Xtensa::F64R_HI, 235,
+ Xtensa::F64S, 236};
static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
index 6d4254a49251..f141a6db02b5 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -107,6 +107,52 @@ def FeatureDebug : SubtargetFeature<"debug", "HasDebug", "true",
def HasDebug : Predicate<"Subtarget->hasDebug()">,
AssemblerPredicate<(all_of FeatureDebug)>;
+def FeatureException : SubtargetFeature<"exception", "HasException", "true",
+ "Enable Xtensa Exception option">;
+def HasException : Predicate<"Subtarget->hasException()">,
+ AssemblerPredicate<(all_of FeatureException)>;
+
+def FeatureHighPriInterrupts : SubtargetFeature<"highpriinterrupts",
+ "HasHighPriInterrupts", "true",
+ "Enable Xtensa HighPriInterrupts option">;
+def HasHighPriInterrupts : Predicate<"Subtarget->hasHighPriInterrupts()">,
+ AssemblerPredicate<(all_of FeatureHighPriInterrupts)>;
+
+def FeatureCoprocessor : SubtargetFeature<"coprocessor", "HasCoprocessor", "true",
+ "Enable Xtensa Coprocessor option">;
+def HasCoprocessor : Predicate<"Subtarget->hasCoprocessor()">,
+ AssemblerPredicate<(all_of FeatureCoprocessor)>;
+
+def FeatureInterrupt : SubtargetFeature<"interrupt", "HasInterrupt", "true",
+ "Enable Xtensa Interrupt option">;
+def HasInterrupt : Predicate<"Subtarget->hasInterrupt()">,
+ AssemblerPredicate<(all_of FeatureInterrupt)>;
+
+def FeatureRelocatableVector : SubtargetFeature<"rvector", "HasRelocatableVector", "true",
+ "Enable Xtensa Relocatable Vector option">;
+def HasRelocatableVector : Predicate<"Subtarget->hasRelocatableVector()">,
+ AssemblerPredicate<(all_of FeatureRelocatableVector)>;
+
+def FeatureTimerInt : SubtargetFeature<"timerint", "HasTimerInt", "true",
+ "Enable Xtensa Timer Interrupt option">;
+def HasTimerInt : Predicate<"Subtarget->hasTimerInt()">,
+ AssemblerPredicate<(all_of FeatureTimerInt)>;
+
+def FeaturePRID : SubtargetFeature<"prid", "HasPRID", "true",
+ "Enable Xtensa Processor ID option">;
+def HasPRID : Predicate<"Subtarget->hasPRID()">,
+ AssemblerPredicate<(all_of FeaturePRID)>;
+
+def FeatureRegionProtection : SubtargetFeature<"regprotect", "HasRegionProtection", "true",
+ "Enable Xtensa Region Protection option">;
+def HasRegionProtection : Predicate<"Subtarget->hasRegionProtection()">,
+ AssemblerPredicate<(all_of FeatureRegionProtection)>;
+
+def FeatureMiscSR : SubtargetFeature<"miscsr", "HasMiscSR", "true",
+ "Enable Xtensa Miscellaneous SR option">;
+def HasMiscSR : Predicate<"Subtarget->hasMiscSR()">,
+ AssemblerPredicate<(all_of FeatureMiscSR)>;
+
//===----------------------------------------------------------------------===//
// Xtensa supported processors.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index 9f641f99de22..378949fa4b02 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -1230,6 +1230,83 @@ let isBarrier = 1, isTerminator = 1 in {
def : Pat<(trap), (BREAK (i32 1), (i32 15))>;
+//===----------------------------------------------------------------------===//
+// Exception feature instructions
+//===----------------------------------------------------------------------===//
+
+def EXCW : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),
+ "excw", []>, Requires<[HasException]> {
+ let r = 0x2;
+ let s = 0x0;
+ let t = 0x8;
+}
+
+def RFDE : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),
+ "rfde", []>, Requires<[HasException]> {
+ let r = 0x3;
+ let s = 0x2;
+ let t = 0x0;
+}
+
+
+def RFE : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),
+ "rfe", []>, Requires<[HasException]> {
+ let r = 0x3;
+ let s = 0x0;
+ let t = 0x0;
+}
+
+def SYSCALL : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),
+ "syscall", []>, Requires<[HasException]> {
+ let r = 0x5;
+ let s = 0x0;
+ let t = 0x0;
+}
+
+//===----------------------------------------------------------------------===//
+// Interrupt feature instructions
+//===----------------------------------------------------------------------===//
+
+def RSIL : RRR_Inst<0x00, 0x00, 0x00, (outs AR:$t), (ins uimm4:$imm),
+ "rsil\t$t, $imm", []>, Requires<[HasInterrupt]> {
+ bits<4> imm;
+
+ let r = 0x6;
+ let s = imm{3-0};
+}
+
+def WAITI : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins uimm4:$imm),
+ "waiti\t$imm", []>, Requires<[HasInterrupt]> {
+ bits<4> imm;
+
+ let r = 0x7;
+ let s = imm{3-0};
+ let t = 0;
+}
+
+def RFI : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins uimm4:$imm),
+ "rfi\t$imm", []>, Requires<[HasInterrupt]> {
+ bits<4> imm;
+
+ let r = 0x3;
+ let s = imm{3-0};
+ let t = 0x1;
+}
+
+//===----------------------------------------------------------------------===//
+// Region Protection feature instructions
+//===----------------------------------------------------------------------===//
+
+def WDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "wdtlb\t$t, $s", []>, Requires<[HasRegionProtection]> {
+ let r = 0xE;
+}
+
+def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "witlb\t$t, $s", []>, Requires<[HasRegionProtection]> {
+ let r = 0x6;
+}
+
//===----------------------------------------------------------------------===//
// DSP Instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
index b5d371c2e315..2fb153d065ac 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
@@ -102,6 +102,8 @@ def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>;
def ATOMCTL : SRReg<99, "atomctl", ["ATOMCTL", "99"]>;
+def DDR : SRReg<104, "ddr", ["DDR", "104"]>;
+
// Instuction break address register 0
def IBREAKA0 : SRReg<128, "ibreaka0", ["IBREAKA0", "128"]>;
@@ -120,20 +122,100 @@ def DBREAKC0 : SRReg<160, "dbreakc0", ["DBREAKC0", "160"]>;
// Data breakpoint control register 1
def DBREAKC1 : SRReg<161, "dbreakc1", ["DBREAKC1", "161"]>;
+def CONFIGID0 : SRReg<176, "configid0", ["CONFIGID0", "176"]>;
+
+// Exception PC1
+def EPC1 : SRReg<177, "epc1", ["EPC1", "177"]>;
+
+// Exception PC2
+def EPC2 : SRReg<178, "epc2", ["EPC2", "178"]>;
+
+// Exception PC3
+def EPC3 : SRReg<179, "epc3", ["EPC3", "179"]>;
+
+// Exception PC4
+def EPC4 : SRReg<180, "epc4", ["EPC4", "180"]>;
+
+// Exception PC5
+def EPC5 : SRReg<181, "epc5", ["EPC5", "181"]>;
+
+// Exception PC6
+def EPC6 : SRReg<182, "epc6", ["EPC6", "182"]>;
+
+// Exception PC7
+def EPC7 : SRReg<183, "epc7", ["EPC7", "183"]>;
+
+def DEPC : SRReg<192, "depc", ["DEPC", "192"]>;
+def EPS2 : SRReg<194, "eps2", ["EPS2", "194"]>;
+def EPS3 : SRReg<195, "eps3", ["EPS3", "195"]>;
+def EPS4 : SRReg<196, "eps4", ["EPS4", "196"]>;
+def EPS5 : SRReg<197, "eps5", ["EPS5", "197"]>;
+def EPS6 : SRReg<198, "eps6", ["EPS6", "198"]>;
+def EPS7 : SRReg<199, "eps7", ["EPS7", "199"]>;
+def CONFIGID1 : SRReg<208, "configid1", ["CONFIGID1", "208"]>;
+def EXCSAVE1 : SRReg<209, "excsave1", ["EXCSAVE1", "209"]>;
+def EXCSAVE2 : SRReg<210, "excsave2", ["EXCSAVE2", "210"]>;
+def EXCSAVE3 : SRReg<211, "excsave3", ["EXCSAVE3", "211"]>;
+def EXCSAVE4 : SRReg<212, "excsave4", ["EXCSAVE4", "212"]>;
+def EXCSAVE5 : SRReg<213, "excsave5", ["EXCSAVE5", "213"]>;
+def EXCSAVE6 : SRReg<214, "excsave6", ["EXCSAVE6", "214"]>;
+def EXCSAVE7 : SRReg<215, "excsave7", ["EXCSAVE7", "215"]>;
+def CPENABLE : SRReg<224, "cpenable", ["CPENABLE", "224"]>;
+
+// Interrupt enable mask register
+def INTSET : SRReg<226, "interrupt", ["INTERRUPT", "226"]>;
+
+def INTCLEAR : SRReg<227, "intclear", ["INTCLEAR", "227"]>;
+
+def INTENABLE : SRReg<228, "intenable", ["INTENABLE", "228"]>;
+
+// Processor State
+def PS : SRReg<230, "ps", ["PS", "230"]>;
+
+// Vector base register
+def VECBASE : SRReg<231, "vecbase", ["VECBASE", "231"]>;
+
+def EXCCAUSE : SRReg<232, "exccause", ["EXCCAUSE", "232"]>;
+
// Cause of last debug exception register
def DEBUGCAUSE : SRReg<233, "debugcause", ["DEBUGCAUSE", "233"]>;
+// Processor Clock Count Register
+def CCOUNT : SRReg<234, "ccount", ["CCOUNT", "234"]>;
+
+// Processor ID Register
+def PRID : SRReg<235, "prid", ["PRID", "235"]>;
+
def ICOUNT : SRReg<236, "icount", ["ICOUNT", "236"]>;
def ICOUNTLEVEL : SRReg<237, "icountlevel", ["ICOUNTLEVEL", "237"]>;
+def EXCVADDR : SRReg<238, "excvaddr", ["EXCVADDR", "238"]>;
+
+// Cycle number to interrupt register 0
+def CCOMPARE0 : SRReg<240, "ccompare0", ["CCOMPARE0", "240"]>;
+
+// Cycle number to interrupt register 1
+def CCOMPARE1 : SRReg<241, "ccompare1", ["CCOMPARE1", "241"]>;
+
+// Cycle number to interrupt register 2
+def CCOMPARE2 : SRReg<242, "ccompare2", ["CCOMPARE2", "242"]>;
+
+def MISC0 : SRReg<244, "misc0", ["MISC0", "244"]>;
+def MISC1 : SRReg<245, "misc1", ["MISC1", "245"]>;
+def MISC2 : SRReg<246, "misc2", ["MISC2", "246"]>;
+def MISC3 : SRReg<247, "misc3", ["MISC3", "247"]>;
def MR01 : RegisterClass<"Xtensa", [i32], 32, (add M0, M1)>;
def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;
def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;
-def SR : RegisterClass<"Xtensa", [i32], 32, (add LBEG, LEND, LCOUNT,
- SAR, BREG, LITBASE, SCOMPARE1, ACCLO, ACCHI, MR, WINDOWBASE, WINDOWSTART,
- IBREAKENABLE, MEMCTL, ATOMCTL, IBREAKA0, IBREAKA1, DBREAKA0, DBREAKA1,
- DBREAKC0, DBREAKC1, DEBUGCAUSE, ICOUNT, ICOUNTLEVEL)>;
+def SR : RegisterClass<"Xtensa", [i32], 32, (add
+ LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, SCOMPARE1, ACCLO, ACCHI, MR,
+ WINDOWBASE, WINDOWSTART, IBREAKENABLE, MEMCTL, ATOMCTL, DDR, IBREAKA0, IBREAKA1,
+ DBREAKA0, DBREAKA1, DBREAKC0, DBREAKC1, CONFIGID0, EPC1, EPC2, EPC3, EPC4, EPC5,
+ EPC6, EPC7, DEPC, EPS2, EPS3, EPS4, EPS5, EPS6, EPS7, CONFIGID1, EXCSAVE1, EXCSAVE2,
+ EXCSAVE3, EXCSAVE4, EXCSAVE5, EXCSAVE6, EXCSAVE7, CPENABLE, INTSET, INTCLEAR, INTENABLE, PS,
+ VECBASE, EXCCAUSE, DEBUGCAUSE, CCOUNT, PRID, ICOUNT, ICOUNTLEVEL, EXCVADDR, CCOMPARE0,
+ CCOMPARE1, CCOMPARE2, MISC0, MISC1, MISC2, MISC3)>;
//===----------------------------------------------------------------------===//
// USER registers
@@ -143,6 +225,8 @@ class URReg<bits<8> num, string n, list<string> alt = []> : XtensaReg<n> {
let AltNames = alt;
}
+def EXPSTATE : URReg<230, "expstate", ["EXPSTATE"]>;
+
// Thread Pointer register
def THREADPTR : URReg<231, "threadptr", ["THREADPTR"]>;
@@ -152,7 +236,7 @@ def F64R_LO : URReg<234, "f64r_lo", ["F64R_LO"]>;
def F64R_HI : URReg<235, "f64r_hi", ["F64R_HI"]>;
def F64S : URReg<236, "f64s", ["F64S"]>;
-def UR : RegisterClass<"Xtensa", [i32], 32, (add THREADPTR, FCR,
+def UR : RegisterClass<"Xtensa", [i32], 32, (add EXPSTATE, THREADPTR, FCR,
FSR, F64R_LO, F64R_HI, F64S)>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
index 800c62d9cefc..8c259dd33f2f 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
@@ -50,6 +50,15 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
HasATOMCTL = false;
HasMEMCTL = false;
HasDebug = false;
+ HasException = false;
+ HasHighPriInterrupts = false;
+ HasCoprocessor = false;
+ HasInterrupt = false;
+ HasRelocatableVector = false;
+ HasTimerInt = false;
+ HasPRID = false;
+ HasRegionProtection = false;
+ HasMiscSR = false;
// Parse features string.
ParseSubtargetFeatures(CPUName, CPUName, FS);
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index eed24f28be15..8eb3281706cf 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -92,6 +92,33 @@ private:
// Enable Xtensa Debug option
bool HasDebug;
+ // Enable Xtensa Exceptions option
+ bool HasException;
+
+ // Enable Xtensa High Priority Interrupt option
+ bool HasHighPriInterrupts;
+
+ // Enable Xtensa Coprocessor option
+ bool HasCoprocessor;
+
+ // Enable Xtensa Interrupt option
+ bool HasInterrupt;
+
+ // Enable Xtensa Relocatable Vector option
+ bool HasRelocatableVector;
+
+ // Enable Xtensa Timer Interrupt option
+ bool HasTimerInt;
+
+ // Enable Xtensa Processor ID option
+ bool HasPRID;
+
+ // Enable Xtensa Region Protection option
+ bool HasRegionProtection;
+
+ // Enable Xtensa Miscellaneous Special Reigsiters option
+ bool HasMiscSR;
+
XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
public:
@@ -145,6 +172,24 @@ public:
bool hasDebug() const { return HasDebug; }
+ bool hasException() const { return HasException; }
+
+ bool hasHighPriInterrupts() const { return HasHighPriInterrupts; }
+
+ bool hasCoprocessor() const { return HasCoprocessor; }
+
+ bool hasInterrupt() const { return HasInterrupt; }
+
+ bool hasRelocatableVector() const { return HasRelocatableVector; }
+
+ bool hasTimerInt() const { return HasTimerInt; }
+
+ bool hasPRID() const { return HasPRID; }
+
+ bool hasRegionProtection() const { return HasRegionProtection; }
+
+ bool hasMiscSR() const { return HasMiscSR; }
+
// Automatically generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
};
diff --git a/llvm/test/MC/Xtensa/xtensa-valid-exc.s b/llvm/test/MC/Xtensa/xtensa-valid-exc.s
new file mode 100644
index 000000000000..4d1e9198bd9a
--- /dev/null
+++ b/llvm/test/MC/Xtensa/xtensa-valid-exc.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc %s -triple=xtensa -mattr=+exception -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+LBL0:
+
+# CHECK-INST: excw
+# CHECK: encoding: [0x80,0x20,0x00]
+ excw
+
+# CHECK-INST: rfde
+# CHECK: encoding: [0x00,0x32,0x00]
+ rfde
+
+# CHECK-INST: rfe
+# CHECK: encoding: [0x00,0x30,0x00]
+ rfe
+
+# CHECK-INST: syscall
+# CHECK: encoding: [0x00,0x50,0x00]
+ syscall
diff --git a/llvm/test/MC/Xtensa/xtensa-valid-int.s b/llvm/test/MC/Xtensa/xtensa-valid-int.s
new file mode 100644
index 000000000000..a24191ef4aa5
--- /dev/null
+++ b/llvm/test/MC/Xtensa/xtensa-valid-int.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=xtensa -mattr=+interrupt -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+
+.align 4
+LBL0:
+
+# CHECK-INST: rfi 1
+# CHECK: encoding: [0x10,0x31,0x00]
+ rfi 1
+
+# CHECK-INST: rsil a3, 1
+# CHECK: encoding: [0x30,0x61,0x00]
+ rsil a3, 1
+
+# CHECK-INST: waiti 1
+# CHECK: encoding: [0x00,0x71,0x00]
+ waiti 1
\ No newline at end of file
diff --git a/llvm/test/MC/Xtensa/xtensa-valid-regprotect.s b/llvm/test/MC/Xtensa/xtensa-valid-regprotect.s
new file mode 100644
index 000000000000..b3504eef1d55
--- /dev/null
+++ b/llvm/test/MC/Xtensa/xtensa-valid-regprotect.s
@@ -0,0 +1,14 @@
+# RUN: llvm-mc %s -triple=xtensa -mattr=+regprotect -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+
+.align 4
+LBL0:
+
+# CHECK-INST: wdtlb a3, a4
+# CHECK: encoding: [0x30,0xe4,0x50]
+ wdtlb a3, a4
+
+# CHECK-INST: witlb a3, a4
+# CHECK: encoding: [0x30,0x64,0x50]
+ witlb a3, a4
--
2.40.1