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the AXI arbiter used extends the AXI id signal. It is used to route things back. output id width = (inputs id width max) + log2up(inputs count) So you need your AXI slaves id width to be bigger i think. |
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Hi, when I use Axi4Upsizer as Axi bus master, I get this compile error:
assertion failed: Expect toplevel/??? : Stream[Axi4Ar] idWidth=4 <= toplevel/[Axi4SharedArbiter]/io_readInputs_0_ar : Stream[Axi4Ar] idWidth=3
there is another master and 3 slaves in Axi bus.
I have tried to remove the Axi4Upsizer type master, then there is no compile error.
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