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add loadHex function for SparseMemory #1014

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hanm2019 opened this issue Jan 12, 2023 · 3 comments · May be fixed by #1015
Open

add loadHex function for SparseMemory #1014

hanm2019 opened this issue Jan 12, 2023 · 3 comments · May be fixed by #1015
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feature ✨ Feature idea with clear API defined good first issue GitHub good first issue need agreement 💬 Waiting for approval to start implementing a feature, or merge a PR

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@hanm2019
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how about add a loadHex function for SparseMemory in lib/src/main/scala/spinal/lib/bus/amba4/axi/sim/AxiMemorySim.scala, so that the memory can be inited both in bin and hex file.
@numero-744 numero-744 added feature ✨ Feature idea with clear API defined need agreement 💬 Waiting for approval to start implementing a feature, or merge a PR good first issue GitHub good first issue labels Jan 12, 2023
@hanm2019 hanm2019 linked a pull request Jan 12, 2023 that will close this issue
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@Dolu1990
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Sure why not ^^

Just one thing which is weird, is that there is currently two implementation of SparseMemory XD

@hanm2019
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Yes, I will try to merge them.

@hanm2019
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@Dolu1990 When I merge these two SparseMemory, I found that the SpinalSimBmbLengthSpliterTester met some problem. I have pick them out.

SpinalHDL/tester/src/test/scala/spinal/tester/scalatest/SpinalSimBmbLengthSpliterTester.scala

Lines 10 to 64 in ad52b69

// test("failed to stop case: only read " ) {
// SimConfig.compile {
// val c = BmbAlignedSpliter(
// ip = BmbAccessParameter(
// addressWidth = 16,
// dataWidth = 32
// ).addSources(16, BmbSourceParameter(
// lengthWidth = 6,
// contextWidth = 3,
// alignmentMin = 0,
// canRead = true,
// canWrite = false,
// alignment = BmbParameter.BurstAlignement.WORD
// )).toBmbParameter(),
// lengthMax = 4
// )
// c
// }.doSimUntilVoid("test") { dut =>
// new BmbBridgeTester(
// master = dut.io.input,
// masterCd = dut.clockDomain,
// slave = dut.io.output,
// slaveCd = dut.clockDomain,
// alignmentMinWidth = dut.ip.access.alignmentMin
// )
// }
// }
// test("Error case: bypass_wr " ) {
// SimConfig.compile {
// val c = BmbAlignedSpliter(
// ip = BmbAccessParameter(
// addressWidth = 16,
// dataWidth = 32
// ).addSources(16, BmbSourceParameter(
// lengthWidth = 6,
// contextWidth = 3,
// alignmentMin = 0,
// canRead = true,
// canWrite = true,
// alignment = BmbParameter.BurstAlignement.WORD
// )).toBmbParameter(),
// lengthMax = 4
// )
// c
// }.doSimUntilVoid("test") { dut =>
// new BmbBridgeTester(
// master = dut.io.input,
// masterCd = dut.clockDomain,
// slave = dut.io.output,
// slaveCd = dut.clockDomain,
// alignmentMinWidth = dut.ip.access.alignmentMin
// )
// }
// }

  1. In the case named failed to stop case: only read , the SparseMemory raises several warning with Page fault while reading page 0 (0x0) which is because the the read address has never write data. and this case can not stop.
  2. In the case named bypass_wr, the testbench also write after read to the memory, and raises an Error on the onRspRead funtion.

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feat: add loadHex function for SparseMemory hanm2019/SpinalHDL
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@Dolu1990 @numero-744 @hanm2019