SpinalSim: onSamplings can't work properly with clock from a blackbox #1334
Comments
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Pinging @wswslzp as they have access to VCS @zyn810039594 please provide a small, self contained example that reproduces the issue so that we have something to run. |
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Sorry for the late reply Here's the code. And this time I simulate on IVerilog, import spinal.core._
import spinal.lib._
import spinal.core.sim._
import spinal.lib.sim.StreamDriver
import scala.util.Random
object MyOnSamplingTest extends App {
case class ClkSource0() extends BlackBox {
val io = new Bundle {
val clk = out Bool ()
}
addRTLPath("./hw/verilog/ClkSource.v")
noIoPrefix()
}
case class ClkSource1() extends BlackBox {
val io = new Bundle {
val clk = out Bool ()
}
noIoPrefix()
}
case class OnSamplingModule() extends Component {
val io = new Bundle {
val rstn = in Bool ()
val sIn = slave(Stream(Bits(16 bits)))
val sOut = master(Stream(Bits(16 bits)))
}
val insideClk0 = ClkSource0()
val insideClk1 = ClkSource1()
insideClk0.io.clk.simPublic()
insideClk1.io.clk.simPublic()
val cd0 = ClockDomain(insideClk0.io.clk, io.rstn)
val cd1 = ClockDomain(insideClk1.io.clk, io.rstn)
val c0Area = new ClockingArea(cd0) {
val streamA = io.sIn.m2sPipe().s2mPipe()
}
val c1Area = new ClockingArea(cd1) {
val streamATemp = cloneOf(io.sIn)
val streamB = streamATemp.halfPipe()
io.sOut << streamB
}
val c0toC1 = StreamFifoCC(c0Area.streamA, c1Area.streamATemp, 2, cd0, cd1)
}
// Low Reset
Config.sim
.compile(OnSamplingModule())
.doSimUntilVoid(dut => {
SimTimeout(10 ms)
dut.io.rstn #= false
sleep(10 us)
dut.io.rstn #= true
val pIn = dut.io.sIn
val pOut = dut.io.sOut
val cd0 = ClockDomain(dut.insideClk0.io.clk, dut.io.rstn)
val cd1 = ClockDomain(dut.insideClk1.io.clk, dut.io.rstn)
val rand = new Random()
var times = 0
pIn.valid #= false
pIn.payload.randomize()
pOut.ready #= false
cd0.onSamplings {
println("pIn valid State = " + pIn.valid.toBoolean)
if (!pIn.valid.toBoolean) {
val randomValue = rand.nextInt()
pIn.valid #= true
pIn.payload #= randomValue
println("In value : " + randomValue)
} else if (pIn.valid.toBoolean && pIn.ready.toBoolean) {
pIn.valid #= false
}
}
cd1.onSamplings {
if (pOut.valid.toBoolean) {
println("Out value : " + pOut.payload.toInt)
pOut.ready.set()
times += 1
if (times == 40) {
simSuccess()
}
} else {
pOut.ready.clear()
}
}
})
}And here's the clock blackbox in Verilog: module ClkSource0(
output wire clk
);
reg clk_r = 0;
always #5.525 clk_r = ~clk_r;
assign clk = clk_r;
endmodule
module ClkSource1(
output wire clk
);
reg clk_r = 0;
always #2.775 clk_r = ~clk_r;
assign clk = clk_r;
endmoduleThe wave is correct, but nothing print in console. |
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What do you mean "missing cycle"? What's the expected behavior? The issue makes no sense to me. |
zyn810039594
changed the title
zyn810039594
changed the title
Sorry for my inaccurate discription, I've change the title of this issue. The problem is, when I simulate with a logic which is driven by a blackbox, the onSamplings function can not work properly. In my example above, |
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Two examples you provide are still compilcated and not small enough I think. I have only noticed that you used some time literal in Verilog source codes without specifing timescale and also using time literal in Spinal testbench. I don't know how VCS or other simulators handle these time literal. These behaviors are somewhat unknown to me. If you think this may relate to simulator API, please help provide the comparison of waveforms coming from VCS and other simulators. |
Okay I'll provide a smaller example later
I think the problem may come from the implementation of onSamplings. In my test, the problem is happened in both VCS and iverilog. I'll have a try in both simulators later. |
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New example: object onSamplingsTest extends App {
case class ClkSource() extends BlackBox {
val io = new Bundle {
val clk = out Bool ()
}
addRTLPath("./hw/verilog/ClkSource.v")
noIoPrefix()
}
case class TestModule() extends Component {
val io = new Bundle {
val rstn = in Bool ()
val testOut = out UInt (8 bits)
}
val clkInst = ClkSource()
clkInst.io.clk.simPublic()
val inCd = ClockDomain(clkInst.io.clk, io.rstn)
val testArea = new ClockingArea(inCd) {
val test = RegInit(U(0, 8 bits))
test := test + 1
io.testOut := test
}
}
Config.sim
.compile(TestModule())
.doSim(dut => {
//Reset
dut.io.rstn #= false
sleep(1 us)
dut.io.rstn #= true
//
ClockDomain(dut.clkInst.io.clk).onSamplings {
println("CountNum: " + dut.io.testOut.toBigInt)
}
sleep(10 us)
simSuccess()
})
}
Clock blackbox written in Verilog (The module ClkSource(
output wire clk
);
reg clk_r = 0;
always #5 clk_r = ~clk_r;
assign clk = clk_r;
endmoduleFor IVerilog: nothing print in console, right wave. For VCS: nothing print in console, right wave. Verilator: can not load simulation model. |
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Looks like none of the simulator works properly for your issue. Try using SystemVerilog TB. SpinalHDL simulation kits may not cover your requirement. Complicated behavior model written in Verilog/SV may not be able to interact with SpinalHDL simulation kits perfectly. |
Spinal version: v1.10.1
Simulation tool: Synopsys VCS 2018
Here's the simulation code:
All the signals here are set with "simPublic".
I want to record the cycles between two transport, but it gives me such a callback:
And the wave is:
Well, it's extremely unexpected... The number of count is obviously wrong, and the char "I" is missing.
The only special is the clock is from a simulation model of an RC osc.
So is there anything wrong about this? Maybe I need to offer a simplified model?
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