privateNamespace changes BlackBox component name

[apstrike]

When using a BlackBox when privateNamespace=true in the SpinalConfig, a prefix is added to the blackboxed module on instantiation.

For example the following code:

class ExBB extends BlackBox {

  val io = new Bundle {
    val clk = in Bool()
    val dout = out Bool()
  }

  mapClockDomain(clock=io.clk)
}

class APExample extends Component {

  val io = new Bundle {
    val dout = out Bool()
  }

  val dut = new ExBB()

  io.dout := dut.io.dout

}

object TestConfig extends SpinalConfig(privateNamespace=true)

object Test {
  def main(args: Array[String]) {

    TestConfig.generateVerilog(new APExample())
  }
}

Produces the following Verilog file:

// Generator : SpinalHDL v1.10.1    git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : APExample
// Git hash  : c48315fc0fad08e65876f209f9cbd59332330ae9

`timescale 1ns/1ps

module APExample (
  output wire          io_dout,
  input  wire          clk
);

  wire                dut_io_dout;

  APExample_ExBB dut (
    .io_clk  (clk        ), //i
    .io_dout (dut_io_dout)  //o
  );
  assign io_dout = dut_io_dout;

endmodule

I’d have assumed that blackboxed modules would keep their names as-is so that a user could share the module across multiple SpinalHDL projects.

[andreasWallner]

If you use privateNamespace then all components are prefixed to prevent any possible clashes when integrating into another codebase.
If you use globalPrefix instead then Blackboxes won't be prefixed:

object TestConfig extends SpinalConfig(globalPrefix="APExample")

Does that work for you?