Register fields with AccessType ROV don't get names

[louiecaulfield]

There's a line in RegInst.field() which causes registers of type ROV to not be named.

This causes trouble when iterating of the bus registers to build a register map.

I don't see the purpose of this line in fact.

[jijingg]

ROV is a new Type for Readonly value different from RO, Which always used for device version ,
ReadOnlyVersion

RO need declare an wire then connect a signal or value to it

val ro_field  = busif.newRegAt(0x0000, "RO TEST").field(Bits(32 bit), RO, 0x0000abcd,  "ro test")
ro_field := B(0x0000abcd, 32 bit)
//ro_field :=  io.read_only_data
busif.newRegAt(0x0004,"ROV test").field(Bits(32 bit), ROV, 0x0FFF1234,  "rov test")

    0x0000:  bus_rdata <=  ro_field;
    0x0004:  bus_rdata <=  32'h0FFF_1234;

assign ro_field = 32'h0000_ABCD