Ping me if you are waiting a feedback/answer to one of your issues :)

[Dolu1990]

No description provided.

[curliph]

vexRiscV support up to 5 pipeline stage. how to configure to instance each stage?
for example, which plugin to instance IF, which to instance DEC and so on...
If I want to instance a RV32IMAC core, 2 pipeline (IF-DEC/DEC-EXE), or 3 pipeline (IF/DEC/EXE),
how to write my configuration?
I known there are many demos , but no detials about pipeline stages.

Thanks for your work.

[Dolu1990]

So basicaly the memory/writeback stages aren't added by plugin, but by the VexRiscvConfig :
https://github.com/SpinalHDL/VexRiscv/blob/dev/src/main/scala/vexriscv/demo/GenTwoThreeStage.scala#L12
see withMemoryStage, withWriteBackStage

Then the fetch stages are added by the IBusSimplePlugin/IBusCachedPlugin,for instance here it specify no fetch stage :
https://github.com/SpinalHDL/VexRiscv/blob/dev/src/main/scala/vexriscv/demo/GenTwoThreeStage.scala#L23

The main limitation is that the decode stage can't be merged in the execute stage currently, but else all can be merged

[curliph]

Thanks a lot, Dolu~

[fatalfeel]

help
#209

[fatalfeel]

need again
#209

[iamkarthikbk]

@Dolu1990 can you please take a look at #215 if you don't mind?

[Saqlinahamad]

Hi @Dolu1990 , Can you please look at #223,
I have deadlines to verify in the board

[Saqlinahamad]

Hi @Dolu1990, #223

[m-pp]

Hi @Dolu1990 , #241

[ldlinh2k]

HI @Dolu1990

[davidwilley]

Hi @Dolu1990 Can you please have a look at #246 ?

[dockside-code]

Hi! @Dolu1990 would you please take a look at #259 ? Thanks!

[hparpinel]

Hi, I am having issues running the demos

[Light9162]

Hi, @Dolu1990 can you assist me on #293?

[xie-1399]

help
#320

[hszilard13]

Hi, can you help me with #357?

[Shris7]

Hi @Dolu1990, can you help me with #369 ?

[ic-hjx]

Hi @Dolu1990 , I have some problem with #406