How to only modify certain one reset kind of specific Reg in vex core.

[littlezpf666]

I need to change a reg reset kind to SYNC in vex core. So, I try to implement by using ClockDomain object according to SpinalHDL docs.

  val decodePc_Domain = ClockDomain(ClockDomain.current.readClockWire,ClockDomain.current.readResetWire,
    config = ClockDomainConfig(
      clockEdge = RISING,
      resetKind = spinal.core.SYNC,
      resetActiveLevel = LOW
    )
  )

  val decodePc_Area = new ClockingArea(decodePc_Domain) {
    val pcReg = Reg(UInt(32 bits)) init (if (resetVector != null) resetVector else externalResetVector) addAttribute (Verilator.public)
  }

But it reports clock crossing violation error now.
CLOCK CROSSING VIOLATION :

• Source : (toplevel/IBusCachedPlugin_decodePc_decodePc_Area_pcReg : UInt[32 bits]) vexriscv.plugin.IBusFetcherImpl$FetchArea$$anonfun$33$$anon$6$$anon$2$$anonfun$34.apply(Fetcher.scala:276)
• Source clock : (toplevel/clk : in Bool)
• Destination : (toplevel/IBusCachedPlugin_fetchPc_pcReg : UInt[32 bits]) vexriscv.plugin.IBusFetcherImpl$FetchArea$$anon$5$$anonfun$30.apply(Fetcher.scala:198)
• Destination clock : (clk : Bool)
  Could you tell me how to only modify one specific Reg's reset kind and how to use clock domain correctly?

[Dolu1990]

Hi,

ClockDomain.current.readClockWire,ClockDomain.current.readResetWire

The following will be detected properly :
ClockDomain.current.clock,ClockDomain.current.reset