The function of Autocomplete and snippets seems not work well on win11

[narutozxp]

terosHDL does not autocomplete port signals when I work in win11， However, terosHDL works well when I connect my Ubuntu server by SSH extension.
Two environments have the same version of terosHDL(v5.0.12)

[ckuhlmann]

I have the same problem on Win 10, TerosHDL v5.0.12 / VSC 1.87.2. I thought this was a limitation of TerosHDL not showing signals, but now that it seems to be a bug, I hope this gets fixed.
It is a rather severe limitation, if there's anything I can do to help narrow the issue down, please let me know.

[gmartina]

Hello @ckuhlmann @narutozxp , I tested it on W11 with v6.0.0 (pre-release) and it works. Please provide a minimal reproducible example (not an image).

[ckuhlmann]

I haven't been able to pinpoint this issue, but one thing that usually causes it, is unsaved file changes. If you add a port or signal and don't save the file, you don't get the autocomplete suggestion for port-maps and inside procedures (inside the very same file). But saving the file and reopening the auto-complete list (ctrl+space), the port/signal is usually there after some time (few seconds). I think this is not due to the language server (using VHDL-LS), as the hover tooltip is available for me without saving the file. I'm not sure whether this is intended behavior / a known limitation, but since the language server works on the unsaved edits, it surely is unexpected from a user point of view.
Not sure whether the the Verilog side of the issue has this in common or is a totally separate issue.

[narutozxp]

@gmartina Hello, there is the example code.
According to the image(OUTlINE), Teros seems to identify the signal name as the signal type.

module misc_ctrl (
	/**********************/
	/*       input        */
	/**********************/
	input  wire        clk_cpu   ,
	input  wire        rst_cpu_n ,
	input       [12:0] nmi_ctrl  ,
	input  wire        int_gpio0, int_gpio1, int_gpio2, int_gpio3,
	input  wire        int_i2c0  ,
	input  wire        int_uart0, int_uart1,
	input  wire        int_spi0  ,
	input  wire        int_timer0, int_timer1, int_timer2, int_timer3,
	input  wire        int_dco, int_dcl,
	input  wire        fpixc, fpofc, fpufc, fpioc, fpdzc, fpidc,
	/**********************/
	/*       output       */
	/**********************/
	output wire [47:0] cpu_int   ,
	output wire        nmi_cpu   ,
	output wire [25:0] stcalib
	// output wire [25:0] irq
);
	localparam  DLY         = 1;
	wire        cpu_exc        ;
	wire [47:0] cpu_int_tmp    ;
	reg  [39:0] int_ff         ;
	reg  [ 1:0] int_des_ff     ;
	reg         int_pvd_ff     ;


	assign stcalib = 26'h752FF;
	assign irq     = |cpu_int_tmp;
	// assign cpu_int = 48'b0;
	assign nmi_cpu = 1'b0;

	assign cpu_int = {34'b0,
		cpu_int_tmp};

	assign cpu_exc = fpixc|fpofc|fpufc|fpioc|fpdzc|fpidc;


	assign cpu_int_tmp = {
		int_dcl 	 ,
		int_dco 	 ,
		int_timer3   ,
		int_timer2   ,
		int_timer1   ,
		int_timer0   ,
		int_gpio3    ,
		int_gpio2    ,
		int_gpio1    ,
		int_gpio0    ,
		int_uart1    ,
		int_uart0    ,
		int_spi0     ,
		int_i2c0
	};

endmodule

[narutozxp]

@gmartina Besides, your demo seems to show the function of vscode itself, not TerosHDL.