"PORT" in the beginning of a VHDL generic name messes up the formatting with Standalone formatter

[am9417]

Describe the bug
If there's a generic that has a string "PORT" in the identifier (e.g. "PORT_COUNT"), running the VHDL formatter with Standalone formatter breaks the file

To Reproduce
Format the following minimal VHDL entity in editor:

entity my_ent is
  generic (PORT_COUNT : natural);
  port(port_ena : bit_vector(PORT_COUNT-1 downto 0));
end entity;

Right click on file and click "Format document" or SHIFT + ALT + F

Expected to have nice formatting, but seems like the port inside a generic name (which should be completely fine!) breaks the formatting and gives a following "formatted" document as output, breaking the VHDL syntax completely.

entity my_ent is
  generic
  (
    port
    _COUNT : natural);
  port
  (
    port_ena : bit_vector(port
    _COUNT - 1 downto 0));
end entity;

Seems like the problem is if the generic starts with "PORT". E.g. "COUNT_PORT" does not trigger this error

Environment information:

• Teros HDL: v5.0.12
• VSCode version:
  • Version: 1.88.0 (user setup)
  • Commit: 5c3e652f63e798a5ac2f31ffd0d863669328dc4c
  • Date: 2024-04-03T13:26:18.741Z
  • Electron: 28.2.8
  • ElectronBuildId: 27744544
  • Chromium: 120.0.6099.291
  • Node.js: 18.18.2
  • V8: 12.0.267.19-electron.0
  • OS: Windows_NT x64 10.0.22631