VHDL code completion improvement (?)

[ungultig1]

Hi there,

One of your best features is the support for vhdl code completion.

However, it could be improved in terms of suggestions that pop up while coding.

I.e.:
Signals defined within a record structure could only be suggested when the record is used,
as at the moment every declaration pops up:

At the moment, TerosHDL is able to distinguish between the declared signals and to whom they belong, as seen for the "u_count (record)" signal.

But, could be even improved to suggest only the mentioned record signal when typing "myRec." record.

Thank you.

PS: Here is the complete code:

library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

entity examp is 
	port(
        i_sl_cnt                  : in std_logic;
        i_sl_reset                  : in std_logic 
	);
end entity examp;

architecture behaviour of examp is   
	type t_myRec is record
        u_count                                 : unsigned(5 downto 0);
	end record;

	signal myRec:	t_myRec;
begin		 

	process(all) begin

        if i_sl_reset then
            myRec.u_count   <= 6d"0";
        end if;

        if i_sl_cnt then
            myRec.u_count   <= myRec.u_count+1;
        end if;

        myRec.

    end process;

end architecture;