Generated files have absolute paths

[shenki]

When building the fusesoc design the files we generate are added to microwatt_0.tcl with an absolute path:

read_verilog {../src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v}
read_verilog {../src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v}
read_vhdl -vhdl2008 {../src/microwatt_0/wishbone_types.vhdl}
read_xdc {../src/microwatt_0/fpga/arty_a7.xdc}
read_vhdl -vhdl2008 {../src/microwatt_0/xilinx-mult-32s.vhdl}
read_xdc {../src/microwatt_0/fpga/fpga-random.xdc}
read_verilog {/home/joel/dev/microwatt/litedram/extras/../generated/arty/litedram_core.v}
read_vhdl -vhdl2008 {/home/joel/dev/microwatt/litedram/extras/../generated/arty/litedram-initmem.vhdl}
read_vhdl -vhdl2008 {/home/joel/dev/microwatt/litedram/extras/../extras/litedram-wrapper-l2.vhdl}
read_verilog {/home/joel/dev/microwatt/liteeth/generated/arty/liteeth_core.v}
read_verilog {/home/joel/dev/microwatt/litesdcard/generated/xilinx/litesdcard_core.v}

set_property include_dirs [list ../src/uart16550_1.5.5-r1/rtl/verilog .] [get_filesets sources_1]
set_property top toplevel [current_fileset]
set_property source_mgmt_mode None [current_project]

This breaks using fusesoc --setup to create the design, and then later building it with vivado in a separate step (perhaps after the git tree has changed, or been moved away).

To replicate:

fusesoc run --setup --build-root test --target=arty_a7-35 microwatt

Investigate how to change the litedram_gen and similar scripts copy the files to the build directory, and to generate relative paths to the files.