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dm_compat.h
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/
dm_compat.h
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#ifndef _DM_COMPAT_H_
#define _DM_COMPAT_H_
#include "miner.h"
#include <linux/i2c-dev.h>
#include <linux/i2c.h>
#include <asm/ioctls.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <ctype.h>
#include <limits.h>
#include <linux/watchdog.h>
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <pthread.h>
#include <linux/spi/spidev.h>
#include <linux/types.h>
#define NUMARGS(...) ((int)(sizeof((int[]){(int)__VA_ARGS__})/sizeof(int)))
#define FSCANF(STREAM, FORMAT, ...) \
do { \
if (unlikely(fscanf((STREAM), (FORMAT), __VA_ARGS__) != NUMARGS(__VA_ARGS__))) { \
applog(LOG_ERR, "Failed to fscanf %d args from %s %s line %d", \
NUMARGS(__VA_ARGS__), __FILE__, __func__, __LINE__); \
} \
} while (0)
#define FREAD(PTR, SIZE, NMEMB, STREAM) \
do { \
if (unlikely(fread((PTR), (SIZE), (NMEMB), (STREAM)) != NMEMB)) \
applog(LOG_ERR, "Failed to fread size %d nmemb %d from %s %s line %d", \
(SIZE), (NMEMB), __FILE__, __func__, __LINE__); \
} while (0)
#define FWRITE(PTR, SIZE, NMEMB, STREAM) \
do { \
if (unlikely(fwrite((PTR), (SIZE), (NMEMB), (STREAM)) != NMEMB)) \
applog(LOG_ERR, "Failed to fwrite size %d nmemb %d from %s %s line %d", \
(SIZE), (NMEMB), __FILE__, __func__, __LINE__); \
} while (0)
#define WRITE(FILDES, BUF, NBYTE) \
do { \
int ret = write((FILDES), (BUF), (NBYTE)); \
if (unlikely(ret != (int)(NBYTE))) { \
if (ret == -1) { \
applog(LOG_ERR, "Failed to write size %d from %s %s line %d with errno %d:%s", \
(NBYTE), __FILE__, __func__, __LINE__, errno, strerror(errno)); \
} else { \
applog(LOG_WARNING, "Failed to write size %d from %s %s line %d", \
(NBYTE), __FILE__, __func__, __LINE__); \
} \
} \
} while (0)
#define READ(FILDES, BUF, NBYTE) \
do { \
int ret = read((FILDES), (BUF), (NBYTE)); \
if (unlikely(ret != (int)(NBYTE))) { \
if (ret == -1) { \
applog(LOG_ERR, "Failed to read size %d from %s %s line %d with errno %d:%s", \
(NBYTE), __FILE__, __func__, __LINE__, errno, strerror(errno)); \
} else { \
applog(LOG_WARNING, "Failed to read size %d from %s %s line %d", \
(NBYTE), __FILE__, __func__, __LINE__); \
} \
} \
} while (0)
/* MCOMPAT_CHAIN */
typedef struct MCOMPAT_CHAIN_TAG{
//
bool (*power_on)(unsigned char);
//
bool (*power_down)(unsigned char);
//
bool (*hw_reset)(unsigned char);
//
bool (*power_on_all)(void);
//
bool (*power_down_all)(void);
}MCOMPAT_CHAIN_T;
void init_mcompat_chain(void);
void exit_mcompat_chain(void);
void register_mcompat_chain(MCOMPAT_CHAIN_T * ops);
bool mcompat_chain_power_on(unsigned char chain_id);
bool mcompat_chain_power_down(unsigned char chain_id);
bool mcompat_chain_hw_reset(unsigned char chain_id);
/* MCOMPAT_FAN */
extern int g_temp_hi_thr;
extern int g_temp_lo_thr;
extern int g_temp_start_thr;
extern int g_dangerous_temp;
extern int g_work_temp;
typedef struct {
int final_temp_avg;
int final_temp_hi;
int final_temp_lo;
int temp_highest[3];
int temp_lowest[3];
}mcompat_temp_s;
typedef struct {
int temp_hi_thr;
int temp_lo_thr;
int temp_start_thr;
int dangerous_stat_temp;
int work_temp;
int default_fan_speed;
}mcompat_temp_config_s;
typedef struct {
int fd;
int last_valid_temp;
int speed;
int last_fan_speed;
int last_fan_temp;
mcompat_temp_s * mcompat_temp;
int temp_average;
int temp_highest;
int temp_lowest;
}mcompat_fan_temp_s;
extern void mcompat_fan_temp_init(unsigned char fan_id,mcompat_temp_config_s temp_config);
extern void mcompat_fan_speed_set(unsigned char fan_id, int speed);
extern void mcompat_fan_speed_update_hub(mcompat_fan_temp_s *fan_temp);
/* MCOMPAT_CMD */
typedef struct MCOMPAT_CMD_TAG{
//
void (*set_speed)(unsigned char, int);
//
bool (*cmd_reset)(unsigned char, unsigned char, unsigned char *, unsigned char *);
//
int (*cmd_bist_start)(unsigned char, unsigned char);
//
bool (*cmd_bist_collect)(unsigned char, unsigned char);
//
bool (*cmd_bist_fix)(unsigned char, unsigned char);
//
bool (*cmd_write_register)(unsigned char, unsigned char, unsigned char *, int);
//
bool (*cmd_read_register)(unsigned char, unsigned char, unsigned char *, int);
//
bool (*cmd_read_write_reg0d)(unsigned char, unsigned char, unsigned char *, int, unsigned char *);
//
bool (*cmd_write_job)(unsigned char, unsigned char, unsigned char *, int);
//
bool (*cmd_read_result)(unsigned char, unsigned char, unsigned char *, int);
//
bool (*cmd_auto_nonce)(unsigned char, int, int);
//
bool (*cmd_read_nonce)(unsigned char, unsigned char *, int);
bool (*cmd_get_temp)(mcompat_fan_temp_s *temp_ctrl);
}MCOMPAT_CMD_T;
void init_mcompat_cmd(void);
void exit_mcompat_cmd(void);
void register_mcompat_cmd(MCOMPAT_CMD_T * cmd_ops_p);
/* MCOMPAT_GPIO */
typedef struct MCOMPAT_GPIO_TAG{
//
void (*set_power_en)(unsigned char, int);
//
void (*set_start_en)(unsigned char, int);
//
bool (*set_reset)(unsigned char, int);
//
void (*set_led)(unsigned char, int);
//
int (*get_plug)(unsigned char);
//
bool (*set_vid)(unsigned char, int);
//
void (*set_green_led)(int mode);
//
void (*set_red_led)(int mode);
//
int (*get_button)(void);
}MCOMPAT_GPIO_T;
void init_mcompat_gpio(void);
void exit_mcompat_gpio(void);
void register_mcompat_gpio(MCOMPAT_GPIO_T * ops);
/* MCOMPAT_GPIO_I2C */
#define _SCL_PIN (0)
#define _SDA_PIN (1)
void mcompat_gpio_i2c_init(void);
void mcompat_gpio_i2c_deinit(void);
void mcompat_gpio_i2c_send_byte(uint8_t data);
uint8_t mcompat_gpio_i2c_recv_byte(void);
bool mcompat_gpio_i2c_send_buf(uint8_t *buf, uint8_t buf_len, uint8_t dev_addr, uint16_t reg_addr);
bool mcompat_gpio_i2c_recv_buf(uint8_t *buf, uint8_t buf_len, uint8_t dev_addr, uint16_t reg_addr);
/* MCOMPAT_PWM */
typedef struct MCOMPAT_PWM_TAG{
//
void (*set_pwm)(unsigned char, int, int);
}MCOMPAT_PWM_T;
void init_mcompat_pwm(void);
void exit_mcompat_pwm(void);
void register_mcompat_pwm(MCOMPAT_PWM_T * ops);
/* MCOMPAT_TEMP */
typedef struct _c_temp
{
short tmp_lo; // lowest temperature
short tmp_hi; // highest temperature
short tmp_avg; // average temperature
bool optimal; // temp considered in optimal range
} c_temp;
extern int mcompat_temp_to_centigrade(int temp);
extern bool mcompat_get_chain_temp(unsigned char chain_id, c_temp *chain_tmp);
extern void mcompat_get_chip_temp(int chain_id, int *chip_temp);
/* MCOMPAT_WATCHDOG */
#define MCOMPAT_WATCHDOG_DEV ("/dev/watchdog0")
void mcompat_watchdog_keep_alive(void);
void mcompat_watchdog_open(void);
void mcompat_watchdog_set_timeout(int timeout);
void mcompat_watchdog_close(void);
/* MCOMPAT_LIB */
#define MCOMPAT_LIB_MINER_TYPE_FILE ("/tmp/type")
#define MCOMPAT_LIB_HARDWARE_VERSION_FILE ("/tmp/hwver")
#define MCOMPAT_LIB_HARDWARE_VERSION_G9 (9)
#define MCOMPAT_LIB_HARDWARE_VERSION_G19 (19)
#define MCOMPAT_LIB_HARDWARE_VERSION_ERR (-1)
#define MCOMPAT_LIB_MINER_TYPE_T1 (1)
#define MCOMPAT_LIB_MINER_TYPE_T2 (2)
#define MCOMPAT_LIB_MINER_TYPE_T3 (3)
#define MCOMPAT_LIB_MINER_TYPE_T4 (4)
#define MCOMPAT_LIB_MINER_TYPE_D11 (5)
#define MCOMPAT_LIB_MINER_TYPE_D12 (6)
#define MCOMPAT_LIB_MINER_TYPE_ERR (-1)
#define MCOMPAT_LIB_VID_VID_TYPE (0)
#define MCOMPAT_LIB_VID_GPIO_I2C_TYPE (1)
#define MCOMPAT_LIB_VID_UART_TYPE (2)
#define MCOMPAT_LIB_VID_I2C_TYPE (3)
#define MCOMPAT_LIB_VID_ERR_TYPE (-1)
#define REG_LENGTH (12)
#define VID_MAX (31)
#define VID_MIN (0)
int mcompat_get_shell_cmd_rst(char *cmd, char *result, int size);
int misc_call_api(char *command, char *host, short int port);
bool misc_tcp_is_ok(char *host, short int port);
char *misc_trim(char *str);
int misc_get_board_version(void);
int misc_get_miner_type(void);
int misc_get_vid_type(void);
void misc_system(const char *cmd, char *rst_buf, int buf_size);
void mcompat_configure_tvsensor(int chain_id, int chip_id, bool is_tsensor);
void mcompat_cfg_tsadc_divider(int chain_id,unsigned int pll_clk);
void mcompat_get_chip_volt(int chain_id, int *chip_volt);
int mcompat_find_chain_vid(int chain_id, int chip_num, int vid_start, double volt_target);
double mcompat_get_average_volt(int *volt, int size);
/* MCOMPAT_DRV */
#define PLATFORM_ZYNQ_SPI_G9 (0x01)
#define PLATFORM_ZYNQ_SPI_G19 (0x02)
#define PLATFORM_ZYNQ_HUB_G9 (0x03)
#define PLATFORM_ZYNQ_HUB_G19 (0x04)
#define PLATFORM_SOC (0x10)
#define PLATFORM_ORANGE_PI (0x20)
#define SPI_SPEED_390K (0)
#define SPI_SPEED_781K (1)
#define SPI_SPEED_1562K (2)
#define SPI_SPEED_3125K (3)
#define SPI_SPEED_6250K (4)
#define SPI_SPEED_9960K (5)
#define MCOMPAT_LOG_DEBUG (1)
#define MCOMPAT_LOG_INFO (2)
#define MCOMPAT_LOG_NOTICE (3)
#define MCOMPAT_LOG_WARNING (4)
#define MCOMPAT_LOG_ERR (5)
#define MCOMPAT_LOG_CRIT (6)
#define MCOMPAT_LOG_ALERT (7)
#define MCOMPAT_LOG_EMERG (8)
extern void sys_platform_debug_init(int debug_level);
extern bool sys_platform_init(int platform, int miner_type, int chain_num, int chip_num);
extern bool sys_platform_exit();
extern bool mcompat_set_spi_speed(unsigned char chain_id, int index);
extern bool mcompat_cmd_reset(unsigned char chain_id, unsigned char chip_id, unsigned char *in, unsigned char *out);
extern int mcompat_cmd_bist_start(unsigned char chain_id, unsigned char chip_id);
extern bool mcompat_cmd_bist_collect(unsigned char chain_id, unsigned char chip_id);
extern bool mcompat_cmd_bist_fix(unsigned char chain_id, unsigned char chip_id);
extern bool mcompat_cmd_write_register(unsigned char chain_id, unsigned char chip_id, unsigned char *reg, int len);
extern bool mcompat_cmd_read_register(unsigned char chain_id, unsigned char chip_id, unsigned char *reg, int len);
extern bool mcompat_cmd_read_write_reg0d(unsigned char chain_id, unsigned char chip_id, unsigned char *in, int len, unsigned char *out);
extern bool mcompat_cmd_read_result(unsigned char chain_id, unsigned char chip_id, unsigned char *res, int len);
extern bool mcompat_cmd_write_job(unsigned char chain_id, unsigned char chip_id, unsigned char *job, int len);
extern bool mcompat_cmd_auto_nonce(unsigned char chain_id, int mode, int len);
extern bool mcompat_cmd_read_nonce(unsigned char chain_id, unsigned char *res, int len);
extern bool mcompat_cmd_get_temp(mcompat_fan_temp_s * fan_temp);
extern bool mcompat_get_chain_temp(unsigned char chain_id, c_temp *chain_tmp);
extern void mcompat_set_power_en(unsigned char chain_id, int val);
extern void mcompat_set_start_en(unsigned char chain_id, int val);
extern bool mcompat_set_reset(unsigned char chain_id, int val);
extern void mcompat_set_led(unsigned char chain_id, int val);
extern bool mcompat_set_vid(unsigned char chain_id, int val);
extern bool mcompat_set_vid_by_step(unsigned char chain_id, int start_vid, int target_vid);
extern void mcompat_set_pwm(unsigned char fan_id, int frequency, int duty);
extern int mcompat_get_plug(unsigned char chain_id);
extern int mcompat_get_button(void);
extern void mcompat_set_green_led(int mode);
extern void mcompat_set_red_led(int mode);
extern bool mcompat_chain_power_on(unsigned char chain_id);
extern bool mcompat_chain_power_down(unsigned char chain_id);
extern bool mcompat_chain_hw_reset(unsigned char chain_id);
extern bool mcompat_chain_power_on_all(void);
extern bool mcompat_chain_power_down_all(void);
#define MCOMPAT_CONFIG_MAX_CHAIN_NUM (8)
#define MCOMPAT_CONFIG_MAX_CHIP_NUM (80)
#define MCOMPAT_CONFIG_MAX_JOB_LEN (92)
#define MCOMPAT_CONFIG_MAX_CMD_LENGTH (256)
#define MAGIC_NUM (100)
#define CMD_BIST_START (0x01)
#define CMD_BIST_COLLECT (0x0b)
#define CMD_BIST_FIX (0x03)
#define CMD_RESET (0x04)
#define CMD_RESETBC (0x05)
#define CMD_WRITE_JOB (0x07)
#define CMD_WRITE_JOB_T1 (0x0c)
#define CMD_READ_RESULT (0x08)
#define CMD_WRITE_REG (0x09)
#define CMD_READ_REG (0x0a)
#define CMD_WRITE_REG0d (0x0d)
#define CMD_POWER_ON (0x02)
#define CMD_POWER_OFF (0x06)
#define CMD_POWER_RESET (0x0c)
#define RESP_READ_REG (0x1a)
#define CMD_ADDR_BROADCAST (0x00)
#define CMD_HL (2)
#define CMD_RESET_DL (4)
#define CMD_RESET_TL (CMD_HL + CMD_RESET_DL)
#define ASIC_MCOMPAT_FAN_PWM_STEP (5)
#define ASIC_MCOMPAT_FAN_PWM_DUTY_MAX (100)
#define ASIC_MCOMPAT_FAN_PWM_FREQ_TARGET (20000)
#define ASIC_MCOMPAT_FAN_PWM_FREQ (20000)
#define FAN_CNT ( 2 )
#define ASIC_MCOMPAT_FAN_TEMP_MAX_THRESHOLD (100)
#define ASIC_MCOMPAT_FAN_TEMP_UP_THRESHOLD (55)
#define ASIC_MCOMPAT_FAN_TEMP_DOWN_THRESHOLD (35)
#define MCOMPAT_VID_UART_PATH ("/dev/ttyPS1")
#define MCOMPAT_CONFIG_CMD_MAX_LEN (MCOMPAT_CONFIG_MAX_JOB_LEN + MCOMPAT_CONFIG_MAX_CHAIN_NUM * 2 * 2)
#define MCOMPAT_CONFIG_CMD_RST_MAX_LEN (MCOMPAT_CONFIG_CMD_MAX_LEN)
/* SPI */
#define MCOMPAT_CONFIG_SPI_DEFAULT_CS_LINE (0)
#define MCOMPAT_CONFIG_SPI_DEFAULT_MODE (SPI_MODE_1)
#define MCOMPAT_CONFIG_SPI_DEFAULT_SPEED (1500000)
#define MCOMPAT_CONFIG_SPI_DEFAULT_BITS_PER_WORD (8)
/* GPIO */
#define MCOMPAT_CONFIG_CHAIN0_POWER_EN_GPIO (872)
#define MCOMPAT_CONFIG_CHAIN1_POWER_EN_GPIO (873)
#define MCOMPAT_CONFIG_CHAIN2_POWER_EN_GPIO (874)
#define MCOMPAT_CONFIG_CHAIN3_POWER_EN_GPIO (875)
#define MCOMPAT_CONFIG_CHAIN4_POWER_EN_GPIO (876)
#define MCOMPAT_CONFIG_CHAIN5_POWER_EN_GPIO (877)
#define MCOMPAT_CONFIG_CHAIN6_POWER_EN_GPIO (878)
#define MCOMPAT_CONFIG_CHAIN7_POWER_EN_GPIO (879)
#define MCOMPAT_CONFIG_CHAIN0_START_EN_GPIO (854)
#define MCOMPAT_CONFIG_CHAIN1_START_EN_GPIO (856)
#define MCOMPAT_CONFIG_CHAIN2_START_EN_GPIO (858)
#define MCOMPAT_CONFIG_CHAIN3_START_EN_GPIO (860)
#define MCOMPAT_CONFIG_CHAIN4_START_EN_GPIO (862)
#define MCOMPAT_CONFIG_CHAIN5_START_EN_GPIO (864)
#define MCOMPAT_CONFIG_CHAIN6_START_EN_GPIO (866)
#define MCOMPAT_CONFIG_CHAIN7_START_EN_GPIO (868)
#define MCOMPAT_CONFIG_CHAIN0_RESET_GPIO (855)
#define MCOMPAT_CONFIG_CHAIN1_RESET_GPIO (857)
#define MCOMPAT_CONFIG_CHAIN2_RESET_GPIO (859)
#define MCOMPAT_CONFIG_CHAIN3_RESET_GPIO (861)
#define MCOMPAT_CONFIG_CHAIN4_RESET_GPIO (863)
#define MCOMPAT_CONFIG_CHAIN5_RESET_GPIO (865)
#define MCOMPAT_CONFIG_CHAIN6_RESET_GPIO (867)
#define MCOMPAT_CONFIG_CHAIN7_RESET_GPIO (869)
#define MCOMPAT_CONFIG_CHAIN0_LED_GPIO (881)
#define MCOMPAT_CONFIG_CHAIN1_LED_GPIO (882)
#define MCOMPAT_CONFIG_CHAIN2_LED_GPIO (883)
#define MCOMPAT_CONFIG_CHAIN3_LED_GPIO (884)
#define MCOMPAT_CONFIG_CHAIN4_LED_GPIO (885)
#define MCOMPAT_CONFIG_CHAIN5_LED_GPIO (886)
#define MCOMPAT_CONFIG_CHAIN6_LED_GPIO (887)
#define MCOMPAT_CONFIG_CHAIN7_LED_GPIO (888)
#define MCOMPAT_CONFIG_CHAIN0_PLUG_GPIO (896)
#define MCOMPAT_CONFIG_CHAIN1_PLUG_GPIO (897)
#define MCOMPAT_CONFIG_CHAIN2_PLUG_GPIO (898)
#define MCOMPAT_CONFIG_CHAIN3_PLUG_GPIO (899)
#define MCOMPAT_CONFIG_CHAIN4_PLUG_GPIO (900)
#define MCOMPAT_CONFIG_CHAIN5_PLUG_GPIO (901)
#define MCOMPAT_CONFIG_CHAIN6_PLUG_GPIO (902)
#define MCOMPAT_CONFIG_CHAIN7_PLUG_GPIO (903)
#define MCOMPAT_CONFIG_B9_GPIO (906 + 51)
#define MCOMPAT_CONFIG_A10_GPIO (906 + 37)
extern int g_platform;
extern int g_miner_type;
extern int g_chain_num;
extern int g_chip_num;
/* ZYNQ_GPIO */
extern void zynq_gpio_init(int pin, int dir);
extern void zynq_gpio_exit(int pin);
extern int zynq_gpio_read(int pin);
/* ZYNQ_PWM */
#define SYSFS_PWM_DEV ("/dev/pwmgen0.0")
#define IOCTL_SET_PWM_FREQ(x) _IOR(MAGIC_NUM, (2*x), char *)
#define IOCTL_SET_PWM_DUTY(x) _IOR(MAGIC_NUM, (2*x+1), char *)
extern void zynq_set_pwm(unsigned char fan_id, int frequency, int duty);
extern int zynq_gpio_g19_vid_set(int chain_id, int level);
/* ZYNQ_SPI */
typedef struct ZYNQ_SPI_TAG{
int fd;
pthread_mutex_t lock;
}ZYNQ_SPI_T;
void zynq_spi_init(ZYNQ_SPI_T *spi, int bus);
void zynq_spi_exit(ZYNQ_SPI_T *spi);
void zynq_spi_read(ZYNQ_SPI_T *spi, uint8_t *rxbuf, int len);
void zynq_spi_write(ZYNQ_SPI_T *spi, uint8_t *txbuf, int len);
void zynq_set_spi_speed(int speed);
/* ZYNQ_VID */
#define SYSFS_VID_DEV ("/dev/vidgen0.0")
#define IOCTL_SET_VAL_0 _IOR(MAGIC_NUM, 0, char *)
#define IOCTL_SET_VALUE_0 _IOR(MAGIC_NUM, 0, char *)
#define IOCTL_SET_CHAIN_0 _IOR(MAGIC_NUM, 1, char *)
typedef struct ZYNQ_VID_TAG{
int fd;
pthread_mutex_t lock;
}ZYNQ_VID_T;
extern int zynq_gpio_g9_vid_set(int level);
extern int zynq_gpio_g19_vid_set(int chain_id, int level);
/* HUB_HARDWARE */
#define _MAX_MEM_RANGE (0x10000)
void hub_hardware_init(void);
void hub_hardware_deinit(void);
/* HUB_VID */
#define I2C_DEVICE_NAME "/dev/i2c-0"
#define I2C_SLAVE_ADDR 0x01
bool hub_set_vid(uint8_t chan_id, int vol);
bool set_timeout_on_i2c(int time);
/* DRV_HUB */
#define PAGE_SIZE ((size_t)getpagesize())*2
#define PAGE_MASK ((uint32_t) (long)~(PAGE_SIZE - 1))
/* Definition for CPU ID */
#define XPAR_CPU_ID 0
/* Definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
/******************************************************************/
/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
/******************************************************************/
#define STDIN_BASEADDRESS 0xE0001000
#define STDOUT_BASEADDRESS 0xE0001000
/******************************************************************/
/* Definitions for peripheral PS7_DDR_0 */
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
/******************************************************************/
/* Definitions for driver DEVCFG */
#define XPAR_XDCFG_NUM_INSTANCES 1
/* Definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
#define XPAR_XDCFG_0_BASEADDR 0xF8007000
#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
/******************************************************************/
/* Definitions for driver DMAPS */
#define XPAR_XDMAPS_NUM_INSTANCES 2
/* Definitions for peripheral PS7_DMA_NS */
#define XPAR_PS7_DMA_NS_DEVICE_ID 0
#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
/* Definitions for peripheral PS7_DMA_S */
#define XPAR_PS7_DMA_S_DEVICE_ID 1
#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DMA_NS */
#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
/* Canonical definitions for peripheral PS7_DMA_S */
#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Definitions for driver EMACPS */
#define XPAR_XEMACPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 1
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 1
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 1
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
/******************************************************************/
/* Canonical definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 1
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 1
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 1
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
/******************************************************************/
/* Definitions for driver FANS_CTRL */
#define XPAR_FANS_CTRL_NUM_INSTANCES 1
/* Definitions for peripheral FANS_CTRL_0 */
#define XPAR_FANS_CTRL_0_DEVICE_ID 0
#define XPAR_FANS_CTRL_0_S00_AXI_BASEADDR 0x43C00000
#define XPAR_FANS_CTRL_0_S00_AXI_HIGHADDR 0x43C0FFFF
/******************************************************************/
/* Definitions for peripheral PS7_AFI_0 */
#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
/* Definitions for peripheral PS7_AFI_1 */
#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
/* Definitions for peripheral PS7_AFI_2 */
#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
/* Definitions for peripheral PS7_AFI_3 */
#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
/* Definitions for peripheral PS7_DDRC_0 */
#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
/* Definitions for peripheral PS7_GLOBALTIMER_0 */
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
/* Definitions for peripheral PS7_GPV_0 */
#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
/* Definitions for peripheral PS7_INTC_DIST_0 */
#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
/* Definitions for peripheral PS7_L2CACHEC_0 */
#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
/* Definitions for peripheral PS7_OCMC_0 */
#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
/* Definitions for peripheral PS7_PL310_0 */
#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
/* Definitions for peripheral PS7_PMU_0 */
#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
/* Definitions for peripheral PS7_RAM_0 */
#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
/* Definitions for peripheral PS7_RAM_1 */
#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
/* Definitions for peripheral PS7_SCUC_0 */
#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
/* Definitions for peripheral PS7_SLCR_0 */
#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
/* Definitions for peripheral PS7_SMCC_0 */
#define XPAR_PS7_SMCC_0_S_AXI_BASEADDR 0xE000E000
#define XPAR_PS7_SMCC_0_S_AXI_HIGHADDR 0xE100EFFF
/******************************************************************/
/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_GPIO_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Definitions for driver MCOMPAT_SPI_WRAPPER */
#define XPAR_MCOMPAT_SPI_WRAPPER_NUM_INSTANCES 1
/* Definitions for peripheral MCOMPAT_SPI_WRAPPER_0 */
#define XPAR_MCOMPAT_SPI_WRAPPER_0_DEVICE_ID 0
#define XPAR_MCOMPAT_SPI_WRAPPER_0_S00_AXI_BASEADDR 0x43C30000
#define XPAR_MCOMPAT_SPI_WRAPPER_0_S00_AXI_HIGHADDR 0x43C3FFFF
/******************************************************************/
/* Definitions for driver NANDPS */
#define XPAR_XNANDPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_NAND_0 */
#define XPAR_PS7_NAND_0_DEVICE_ID 0
#define XPAR_PS7_NAND_0_BASEADDR 0xE1000000
#define XPAR_PS7_NAND_0_HIGHADDR 0xE1000FFF
#define XPAR_PS7_NAND_0_NAND_CLK_FREQ_HZ 100000000
#define XPAR_PS7_NAND_0_SMC_BASEADDR 0xE000E000
#define XPAR_PS7_NAND_0_NAND_WIDTH 8
/******************************************************************/
/* Canonical definitions for peripheral PS7_NAND_0 */
#define XPAR_XNANDPS_0_DEVICE_ID XPAR_PS7_NAND_0_DEVICE_ID
#define XPAR_XNANDPS_0_CPU_BASEADDR 0xE1000000
#define XPAR_XNANDPS_0_CPU_HIGHADDR 0xE1000FFF
#define XPAR_XNANDPS_0_NAND_CLK_FREQ_HZ 100000000
#define XPAR_XNANDPS_0_SMC_BASEADDR 0xE000E000
#define XPAR_XNANDPS_0_NAND_WIDTH 8
/******************************************************************/
/* Definitions for driver READ_DNA */
#define XPAR_READ_DNA_NUM_INSTANCES 1
/* Definitions for peripheral READ_DNA_0 */
#define XPAR_READ_DNA_0_DEVICE_ID 0
#define XPAR_READ_DNA_0_S00_AXI_BASEADDR 0x43C20000
#define XPAR_READ_DNA_0_S00_AXI_HIGHADDR 0x43C2FFFF
/******************************************************************/
/* Definitions for driver SCUGIC */
#define XPAR_XSCUGIC_NUM_INSTANCES 1U
/* Definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_SCUGIC_0_DEVICE_ID 0U
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
/******************************************************************/
/* Definitions for driver SCUTIMER */
#define XPAR_XSCUTIMER_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUTIMER_0 */
#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
/******************************************************************/
/* Definitions for driver SCUWDT */
#define XPAR_XSCUWDT_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Definitions for driver SDPS */
#define XPAR_XSDPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SD_0 */
#define XPAR_PS7_SD_0_DEVICE_ID 0
#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 100000000
#define XPAR_PS7_SD_0_HAS_CD 0
#define XPAR_PS7_SD_0_HAS_WP 0
#define XPAR_PS7_SD_0_BUS_WIDTH 0
#define XPAR_PS7_SD_0_MIO_BANK 0
#define XPAR_PS7_SD_0_HAS_EMIO 0
/******************************************************************/
/* Canonical definitions for peripheral PS7_SD_0 */
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
#define XPAR_XSDPS_0_BASEADDR 0xE0100000
#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 100000000
#define XPAR_XSDPS_0_HAS_CD 0
#define XPAR_XSDPS_0_HAS_WP 0
#define XPAR_XSDPS_0_BUS_WIDTH 0
#define XPAR_XSDPS_0_MIO_BANK 0
#define XPAR_XSDPS_0_HAS_EMIO 0
/******************************************************************/
/* Definitions for driver UARTPS */
#define XPAR_XUARTPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_UART_1 */
#define XPAR_PS7_UART_1_DEVICE_ID 0
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000
#define XPAR_PS7_UART_1_HAS_MODEM 0
/******************************************************************/