Note that changing the c$ prefix doesn't help; if you use an implicit clock, the argument is named like $d(%,%) which maps to the basic Verilog identifier _$d_0 exhibiting the same issue.

Here's a small reproducer

module ImplClock where
​
import Clash.Prelude
​
topEntity ::
  HiddenClock System =>
  Signal System (Unsigned 8) ->
  Signal System (Unsigned 8)
topEntity = dflipflop
{-# NOINLINE topEntity #-}

Note that this issue means f6a25e0 was an incomplete fix, as it only fixed VHDL, but not Verilog.

We're going to work on fixing this at ZuriHac

Changing the ID generation is indeed a little hairy here. The identifiers which cause problems ultimately come from unsafeFromCoreId, meaning we don't do the sanitising that we get from makeBasic etc. We probably don't want to just change this function to strip out characters like $ because some names might be specified by users directly in things like synthesize annotations.

Perhaps a solution could be to add a flag to actually do this mangling, i.e. -fclash-sanitise-netlist-ids, which does this stripping of potentially troublesome characters with the caveat that user-specified names that end up going through unsafeFromCoreId may no longer stay as exactly what the user specified.