vioProbe does not handle zero-width probes gracefully

[martijnbastiaan]

This:

commit b1ff577f247c98fd0422a5e59013c9c8e80c227d (HEAD -> master)
Author: Martijn Bastiaan <martijn@qbaylogic.com>
Date:   Wed Feb 7 17:21:14 2024 +0100

    Add tests for #2661

diff --git a/tests/Main.hs b/tests/Main.hs
index b56019fe9..650fc2502 100755
--- a/tests/Main.hs
+++ b/tests/Main.hs
@@ -559,7 +559,9 @@ runClashTest = defaultMain $ clashTestRoot
                   def{ hdlTargets=[VHDL, Verilog, SystemVerilog]
                      , hdlLoad=[Vivado]
                      , hdlSim=[Vivado]
-                     , buildTargets=BuildSpecific [ "noInputTrue"
+                     , buildTargets=BuildSpecific [ "t2661arg"
+                                                  , "t2661res"
+                                                  , "noInputTrue"
                                                   , "noInputFalse"
                                                   , "noInputLow"
                                                   , "noInputHigh"
diff --git a/tests/shouldwork/Cores/Xilinx/VIO.hs b/tests/shouldwork/Cores/Xilinx/VIO.hs
index 483ebc32e..88553fe57 100644
--- a/tests/shouldwork/Cores/Xilinx/VIO.hs
+++ b/tests/shouldwork/Cores/Xilinx/VIO.hs
@@ -28,6 +28,27 @@ top = 0
 
 makeTopEntity 'top
 
+t2661arg ::
+  "clk" ::: Clock Dom ->
+  "zero" ::: Signal Dom () ->
+  "result" ::: Signal Dom Bool
+t2661arg = vioProbe @Dom inNames outNames True
+ where
+  inNames = singleton "probe_in"
+  outNames = singleton "probe_out"
+{-# ANN t2661arg (TestBench 'top) #-}
+makeTopEntity 't2661arg
+
+t2661res ::
+  "clk" ::: Clock Dom ->
+  "result" ::: Signal Dom (Bool, ())
+t2661res = vioProbe @Dom inNames outNames (True, ())
+ where
+  inNames = Nil
+  outNames = "probe_out" :> "probe_out_zero" :> Nil
+{-# ANN t2661res (TestBench 'top) #-}
+makeTopEntity 't2661res
+
 noInputTrue ::
   "clk" ::: Clock Dom ->
   "result" ::: Signal Dom Bool

makes

cabal run clash-testsuite -- -p shouldwork.Cores.Xilinx.VIO.VHDL

fail with

Clash error call:
Number of input names did not match number of input probes. Expected
0 input name(s), got 1. Got input
name(s):

  [ "probe_in" ]
CallStack (from HasCallStack):
  error, called at src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs:147:9 in clash-cores-1.9.0-inplace:Clash.Cores.Xilinx.VIO.Internal.BlackBoxes
  vioProbeBBTF, called at src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs:111:5 in clash-cores-1.9.0-inplace:Clash.Cores.Xilinx.VIO.Internal.BlackBoxes
  vioProbeTF, called at src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs:85:41 in clash-cores-1.9.0-inplace:Clash.Cores.Xilinx.VIO.Internal.BlackBoxes
  vioProbeBBF, called at <interactive>:2:1 in interactive:Ghci1

for t2661arg, and fails with

Clash error call:
Number of output names did not match number of output probes. Expected
1 output name(s), got 2. Got output
name(s):

  [ "probe_out" , "probe_out_zero" ]
CallStack (from HasCallStack):
  error, called at src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs:156:9 in clash-cores-1.9.0-inplace:Clash.Cores.Xilinx.VIO.Internal.BlackBoxes
  vioProbeBBTF, called at src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs:111:5 in clash-cores-1.9.0-inplace:Clash.Cores.Xilinx.VIO.Internal.BlackBoxes
  vioProbeTF, called at src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs:85:41 in clash-cores-1.9.0-inplace:Clash.Cores.Xilinx.VIO.Internal.BlackBoxes
  vioProbeBBF, called at <interactive>:2:1 in interactive:Ghci1

for t2661res